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| REJ09B0337-0200 8 38K0 Group User's Manual RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev. 2.00 Revision date: Oct 05, 2006 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. BEFORE USING THIS MANUAL This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter. 1. Organization q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : (Note 2) Bits b7 b6 b5 b4 b3 b2 b1 b0 0 Bit attributes (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 3B 16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 0 0 1 Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected : Bit in which nothing is arranged : Bit that is not used for control of the corresponding function Note 1:. Contents immediately after reset release 0....... "0" at reset release 1....... "1" at reset release ?....... Undefined at reset release .......Contents determined by option at reset release Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows : R....... Read ...... Read enabled .......Read disabled W......Write ..... Write enabled ...... Write disabled ......."0" write 3. Supplementation For details of software, refer to the "740 FAMILY SOFTWARE MANUAL." For details of development support tools, refer to the "Renesas Technology" Homepage (http://www.renesas.com). Table of contents 38K0 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................... 2 FEATURES ......................................................................................................................................... 2 PIN CONFIGURATION ..................................................................................................................... 2 FUNCTIONAL BLOCK ..................................................................................................................... 3 PIN DESCRIPTION ........................................................................................................................... 4 PART NUMBERING .......................................................................................................................... 5 GROUP EXPANSION ....................................................................................................................... 6 Memory Type ............................................................................................................................... 6 Memory Size ................................................................................................................................ 6 Packages ...................................................................................................................................... 6 FUNCTIONAL DESCRIPTION ......................................................................................................... 7 Central Processing Unit (CPU) ................................................................................................. 7 Memory ....................................................................................................................................... 11 I/O Ports ..................................................................................................................................... 13 Interrupts .................................................................................................................................... 17 Timers ......................................................................................................................................... 20 Serial Interface .......................................................................................................................... 22 USB Function ............................................................................................................................. 26 External Bus Interface (EXB) .................................................................................................. 52 Multichannel RAM ..................................................................................................................... 71 A/D Converter ............................................................................................................................ 73 Watchdog Timer ........................................................................................................................ 75 Reset Circuit .............................................................................................................................. 76 PLL Circuit (Frequency Synthesizer) ...................................................................................... 77 Clock Generating Circuit .......................................................................................................... 79 Flash Memory Mode ................................................................................................................. 82 NOTES ON PROGRAMMING ...................................................................................................... 108 NOTES ON USAGE ...................................................................................................................... 110 DATA REQUIRED FOR MASK ORDERS ................................................................................. 110 FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 111 CHAPTER 2 APPLICATION 2.1 I/O port ........................................................................................................................................ 2 2.1.1 Memory map ...................................................................................................................... 2 2.1.2 Related registers ............................................................................................................... 3 2.1.3 Handling of unused pins .................................................................................................. 5 2.1.4 Notes on input and output pins ...................................................................................... 6 2.1.5 Termination of unused pins ............................................................................................. 7 2.2 Interrupt ...................................................................................................................................... 8 2.2.1 Memory map ...................................................................................................................... 8 2.2.2 Related registers ............................................................................................................... 8 2.2.3 Interrupt source ............................................................................................................... 11 2.2.4 Interrupt operation ........................................................................................................... 12 2.2.5 Interrupt control ............................................................................................................... 15 2.2.6 INT interrupt ..................................................................................................................... 18 2.2.7 Key input interrupt .......................................................................................................... 19 2.2.8 Notes on interrupts ......................................................................................................... 21 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 1 of 13 Table of contents 38K0 Group 2.3 Timer .......................................................................................................................................... 23 2.3.1 Memory map .................................................................................................................... 23 2.3.2 Related registers ............................................................................................................. 23 2.3.3 Timer application examples ........................................................................................... 28 2.3.4 Notes on timer ................................................................................................................. 39 2.4 Serial I/O ................................................................................................................................... 40 2.4.1 Memory map .................................................................................................................... 40 2.4.2 Related registers ............................................................................................................. 41 2.4.3 Serial I/O connection examples .................................................................................... 45 2.4.4 Setting of serial I/O transfer data format .................................................................... 47 2.4.5 Serial I/O application examples .................................................................................... 48 2.4.6 Notes on serial I/O ......................................................................................................... 66 2.5 USB function ........................................................................................................................... 69 2.6 External bus interface(EXB) ................................................................................................. 70 2.7 A/D converter .......................................................................................................................... 71 2.7.1 Memory map .................................................................................................................... 71 2.7.2 Related registers ............................................................................................................. 71 2.7.3 A/D converter application examples ............................................................................. 74 2.7.4 Notes on A/D converter ................................................................................................. 76 2.8 Watchdog timer ....................................................................................................................... 77 2.8.1 Memory map .................................................................................................................... 77 2.8.2 Related registers ............................................................................................................. 77 2.8.3 Watchdog timer application examples ........................................................................ 79 2.8.4 Notes on watchdog timer ............................................................................................... 80 2.9 Reset .......................................................................................................................................... 81 2.9.1 Connection example of reset IC ................................................................................... 81 ____________ 2.9.2 Notes on RESET pin ...................................................................................................... 82 2.10 Frequency synthesizer (PLL) ............................................................................................. 83 2.10.1 Memory map .................................................................................................................. 83 2.10.2 Related registers ........................................................................................................... 83 2.10.3 Functional description ................................................................................................... 85 2.10.4 Notes on PLL ................................................................................................................ 88 2.11 Clock generating circuit ..................................................................................................... 89 2.11.1 Memory map .................................................................................................................. 89 2.11.2 Related registers ........................................................................................................... 89 2.11.3 Oscillation control .......................................................................................................... 91 2.12 Standby function .................................................................................................................. 94 2.12.1 Memory map .................................................................................................................. 94 2.12.2 Related registers ........................................................................................................... 94 2.12.3 Stop mode ...................................................................................................................... 95 2.12.4 Wait mode ...................................................................................................................... 99 2.12.5 Notes on stand-by function ........................................................................................ 101 2.13 Flash memory ...................................................................................................................... 102 2.13.1 Overview ....................................................................................................................... 102 2.13.2 Memory map ................................................................................................................ 102 2.13.3 Related registers ......................................................................................................... 103 2.13.4 Parallel I/O mode ........................................................................................................ 104 2.13.5 Standard serial I/O mode ........................................................................................... 104 2.13.6 CPU rewrite mode ...................................................................................................... 105 2.13.7 Flash memory mode application examples ............................................................. 106 2.13.8 Notes on CPU rewrite mode ..................................................................................... 111 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 2 of 13 Table of contents 38K0 Group CHAPTER 3 APPENDIX 3.1 Electrical characteristics ........................................................................................................ 2 3.1.1 Absolute maximum ratings ............................................................................................... 2 3.1.2 Recommended operating conditions ............................................................................... 3 3.1.3 Electrical characteristics ................................................................................................... 5 3.1.4 A/D converter characteristics ........................................................................................... 7 3.1.5 Timing requirements ......................................................................................................... 8 3.1.6 Switching characteristics ................................................................................................ 11 3.2 Notes on use ........................................................................................................................... 20 3.2.1 Notes on input and output ports ................................................................................... 20 3.2.2 Termination of unused pins ........................................................................................... 21 3.2.3 Notes on interrupts ......................................................................................................... 22 3.2.4 Notes on timer ................................................................................................................. 23 3.2.5 Notes on serial I/O ......................................................................................................... 24 3.2.6 Notes on USB function ................................................................................................... 26 3.2.7 Notes on A/D converter ................................................................................................ 27 3.2.8 Notes on _____________ timer ............................................................................................... 27 watchdog 3.2.9 Notes on RESET pin ...................................................................................................... 27 3.2.10 Notes onPLL .................................................................................................................. 27 3.2.11 Notes on stand-by function .......................................................................................... 28 3.2.12 Notes on CPU rewrite mode ....................................................................................... 28 3.2.13 Notes on programming ................................................................................................. 29 3.2.14 Notes on flash memory version .................................................................................. 31 3.2.15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs .............................................................................................................................. 31 3.3 Countermeasures against noise ......................................................................................... 32 3.3.1 Shortest wiring length ..................................................................................................... 32 3.3.2 Connection of bypass capacitor across VSS line and VCC line .................................. 34 3.3.3 Wiring to analog input pins ........................................................................................... 35 3.3.4 Oscillator concerns .......................................................................................................... 36 3.3.5 Setup for I/O ports .......................................................................................................... 37 3.3.6 Providing of watchdog timer function by software ..................................................... 38 3.4 List of registers ...................................................................................................................... 39 3.5 Package outline ...................................................................................................................... 73 3.6 Machine instructions ............................................................................................................. 75 3.7 List of instruction code ........................................................................................................ 87 3.8 SFR memory map ................................................................................................................... 88 3.9 Pin configurations .................................................................................................................. 89 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 3 of 13 List of figures 38K0 Group List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of 38K0 group ........................................................................................ 2 2 Functional block diagram .................................................................................................... 3 3 Part numbering ..................................................................................................................... 5 4 Memory expansion plan ...................................................................................................... 6 5 740 Family CPU register structure .................................................................................... 7 6 Register push and pop at interrupt generation and subroutine call ............................. 8 7 Structure of CPU mode register ...................................................................................... 10 8 Memory map diagram ........................................................................................................ 11 9 Memory map of special function register (SFR) ............................................................ 12 10 Port block diagram (1) .................................................................................................... 14 11 Port block diagram (2) .................................................................................................... 15 12 Structure of port I/O-related registers ........................................................................... 16 13 Interrupt control ................................................................................................................ 18 14 Structure of interrupt-related registers .......................................................................... 18 15 Connection example when using key input interrupt and port P0 block diagram .. 19 16 Structure of timer X mode register ............................................................................... 20 17 Timer block diagram ........................................................................................................ 21 18 Block diagram of clock synchronous serial I/O ........................................................... 22 19 Operation of clock synchronous serial I/O function .................................................... 22 20 Block diagram of UART serial I/O ................................................................................. 23 21 Operation of UART serial I/O function .......................................................................... 23 22 Structure of serial I/O control registers ........................................................................ 25 23 USB function overview .................................................................................................... 26 24 USB Function Control Circuit (USBFCC) block diagram ............................................ 27 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V VCC 5.25V) ........................................................................................................................... 28 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V VCC 4.0V) ............................................................................................................................. 28 27 Example setting of buffer area beginning address ..................................................... 29 28 Examples of interrupt source dependant buffer area offset address ....................... 29 29 USB device interrupt control .......................................................................................... 31 30 USB related registers ...................................................................................................... 32 31 Structure of USB control register .................................................................................. 33 32 Structure of USB function enable register ................................................................... 33 33 Structure of USB function address register ................................................................. 34 34 Structure of Frame number register Low ..................................................................... 34 35 Structure of Frame number register High .................................................................... 34 36 Structure of USB interrupt source enable register ...................................................... 35 37 Structure of USB interrupt source register ................................................................... 36 38 Structure of Endpoint index register ............................................................................. 36 39 Structure of EP00 stage register ................................................................................... 37 40 Structure of EP00 control register 1 ............................................................................. 37 41 Structure of EP00 control register 2 ............................................................................. 37 42 Structure of EP00 control register 3 ............................................................................. 38 43 Structure of EP00 interrupt source register ................................................................. 38 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 4 of 13 List of figures 38K0 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Structure of EP00 byte number register ....................................................................... 39 Structure of EP00 buffer area set register ................................................................... 39 Structure of EP01 set register ....................................................................................... 40 Structure of EP01 control register 1 ............................................................................. 40 Structure of EP01 control register 2 ............................................................................. 41 Structure of EP01 control register 3 ............................................................................. 41 Structure of EP01 interrupt source register ................................................................. 41 Structure of EP01 byte number register 0 ................................................................... 42 Structure of EP01 byte number register 1 ................................................................... 42 Structure of EP01 MAX. packet size register .............................................................. 42 Structure of EP01 buffer area set register ................................................................... 43 Structure of EP02 set register ....................................................................................... 44 Structure of EP02 control register 1 ............................................................................. 44 Structure of EP02 control register 2 ............................................................................. 45 Structure of EP02 control register 3 ............................................................................. 45 Structure of EP02 interrupt source register ................................................................. 45 Structure of EP02 byte number register 0 ................................................................... 46 Structure of EP02 byte number register 1 ................................................................... 46 Structure of EP02 MAX. packet size register .............................................................. 46 Structure of EP02 buffer area set register ................................................................... 47 Structure of EP03 set register ....................................................................................... 48 Structure of EP03 control register 1 ............................................................................. 48 Structure of EP03 control register 2 ............................................................................. 49 Structure of EP03 control register 3 ............................................................................. 49 Structure of EP03 interrupt source register ................................................................. 49 Structure of EP03 byte number register 0 ................................................................... 50 Structure of EP03 byte number register 1 ................................................................... 50 Structure of EP03 MAX. packet size register .............................................................. 50 Structure of EP03 buffer area set register ................................................................... 51 External bus interface ..................................................................................................... 52 Data transfer timing of memory channel ...................................................................... 52 External bus interface (EXB) pin assignment .............................................................. 53 Block diagram of external bus interface (EXB) ........................................................... 54 EXB related registers (1) ................................................................................................ 58 EXB related registers (2) ................................................................................................ 58 Structure of EXB interrupt source enable register ...................................................... 59 Structure of EXB interrupt source register ................................................................... 59 Structure of EXB index register ..................................................................................... 60 Structure of Register window 1 ..................................................................................... 60 Structure of Register window 2 ..................................................................................... 60 Index00[low]; Structure of External I/O configuration register ................................... 61 Index00[high]; Structure of External I/O configuration register ................................ 61 Index01[low]; Structure of Transmit/Receive buffer register ...................................... 62 Index02[low]; Structure of Memory channel operation mode register ...................... 62 Index03[low]; Structure of Memory address counter .................................................. 62 Index03[high]; Structure of Memory address counter ................................................. 63 Index04[low]; Structure of End address register ......................................................... 63 Index04[high]; Structure of End address register ........................................................ 63 CPU channel receiving operation .................................................................................. 64 CPU channel tranmitting operation ................................................................................ 65 Memory channel receiving operation (1) ...................................................................... 66 Memory channel receiving operation (2) ...................................................................... 67 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 5 of 13 List of figures 38K0 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 96 Memory channel receiving operation (3) ...................................................................... 68 97 Memory channel tranmitting operation (1) .................................................................... 69 98 Memory channel tranmitting operation (2) .................................................................... 70 99 Multichannel RAM timing diagram (no wait) ................................................................ 71 100 Multichannel RAM timing diagram (one wait) ............................................................ 71 101 Multichannel RAM operation example ......................................................................... 72 102 Structure of AD control register ................................................................................... 73 103 10-bit A/D mode reading .............................................................................................. 73 104 A/D converter block diagram ........................................................................................ 74 105 Block diagram of Watchdog timer ............................................................................... 75 106 Structure of Watchdog timer control register ............................................................. 75 108 Reset sequence ............................................................................................................. 76 107 Example of reset circuit ................................................................................................ 76 109 Block diagram of PLL circuit ........................................................................................ 77 110 Structure of PLL control register ................................................................................. 78 111 Ceramic resonator or quartz-crystal oscilltor circuit ................................................. 80 112 External clock input circuit ........................................................................................... 80 114 System clock generating circuit block diagram (single-chip mode) ........................ 80 113 Structure of MISRG ....................................................................................................... 80 115 State transitions of clock .............................................................................................. 81 116 Block diagram of built-in flash memory ...................................................................... 83 117 Structure of flash memory control register ................................................................. 84 118 CPU rewrite mode set/release flowchart .................................................................... 85 119 Program flowchart .......................................................................................................... 87 120 Erase flowchart .............................................................................................................. 88 121 Full status check flowchart and remedial procedure for errors .............................. 90 122 Structure of ROM code protect control register ........................................................ 91 123 ID code store addresses .............................................................................................. 92 124 Pin connection diagram in standard serial I/O mode (1) ......................................... 96 125 Timing for page read ..................................................................................................... 98 126 Timing for reading status register ............................................................................... 98 127 Timing for clear status register .................................................................................... 99 128 Timing for page program .............................................................................................. 99 129 Timing for erase all blocks ......................................................................................... 100 130 Timing for download .................................................................................................... 101 131 Timing for version information output ....................................................................... 102 132 Timing for Boot ROM area output ............................................................................. 102 133 Timing for ID check ..................................................................................................... 103 134 ID code storage addresses ........................................................................................ 103 135 Full status check flowchart and remedial procedure for errors ............................ 106 136 Example circuit application for standard serial I/O mode ...................................... 107 137 Definition of A/D conversion accuracy ...................................................................... 109 138 A/D conversion equivalent circuit .............................................................................. 112 139 A/D conversion timing chart ....................................................................................... 112 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 6 of 13 List of figures 38K0 Group CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2 2.1.2 Structure of Port Pi (i = 0 to 6) .................................................................................... 3 2.1.3 Structure of Port Pi direction register (i = 0 to 6) ..................................................... 3 2.1.4 Structure of Port P0 pull-up control register ............................................................... 4 2.1.5 Structure of Port P5 pull-up control register ............................................................... 4 2.2.1 Memory map of registers related to interrupt ............................................................. 8 2.2.2 Structure of Interrupt request register 1 ...................................................................... 8 2.2.3 Structure of Interrupt request register 2 ...................................................................... 9 2.2.4 Structure of Interrupt control register 1 ....................................................................... 9 2.2.5 Structure of Interrupt control register 2 ..................................................................... 10 2.2.6 Structure of Interrupt edge selection register ........................................................... 10 2.2.7 Interrupt operation diagram .......................................................................................... 12 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request ........................................................................................................................................ 13 2.2.9 Time up to execution of interrupt processing routine .............................................. 14 2.2.10 Timing chart after acceptance of interrupt request .............................................. 14 2.2.11 Interrupt control diagram ............................................................................................ 15 2.2.12 Example of multiple interrupts ................................................................................... 17 2.2.13 Connection example and port P0 block diagram when using key input interrupt . ...................................................................................................................................... 19 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13) . ...................................................................................................................................... 20 2.2.15 Sequence of changing relevant register .................................................................. 21 2.2.16 Sequence of check of interrupt request bit ............................................................. 22 2.3.1 Memory map of registers related to timers ............................................................... 23 2.3.2 Structure of Prescaler 12, Prescaler X ...................................................................... 23 2.3.3 Structure of Timer 1 ..................................................................................................... 24 2.3.4 Structure of Timer 2, Timer X ..................................................................................... 24 2.3.5 Structure of Timer X mode register ............................................................................ 25 2.3.6 Structure of Interrupt request register 1 .................................................................... 26 2.3.7 Structure of Interrupt request register 2 .................................................................... 26 2.3.8 Structure of Interrupt control register 1 ..................................................................... 27 2.3.9 Structure of Interrupt control register 2 ..................................................................... 27 2.3.10 Timers connection and setting of division ratios .................................................... 29 2.3.11 Related registers setting ............................................................................................ 29 2.3.12 Control procedure ........................................................................................................ 30 2.3.13 Peripheral circuit example .......................................................................................... 31 2.3.14 Timers connection and setting of division ratios .................................................... 31 2.3.15 Related registers setting ............................................................................................ 32 2.3.16 Control procedure ........................................................................................................ 32 2.3.17 Judgment method of valid/invalid of input pulses .................................................. 33 2.3.18 Related registers setting ............................................................................................ 34 2.3.19 Control procedure ........................................................................................................ 35 2.3.20 Timers connection and setting of division ratios .................................................... 36 2.3.21 Related registers setting ............................................................................................ 37 2.3.22 Control procedure ........................................................................................................ 38 2.4.1 Memory map of registers related to Serial I/O ......................................................... 40 2.4.2 Structure of Transmit/Receive buffer register ........................................................... 41 2.4.3 Structure of Serial I/O status register ........................................................................ 41 2.4.4 Structure of Serial I/O control register ....................................................................... 42 2.4.5 Structure of UART control register ............................................................................. 42 page 7 of 13 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 List of figures 38K0 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.6 Structure of Baud rate generator ................................................................................ 43 2.4.7 Structure of Interrupt edge selection register ........................................................... 43 2.4.8 Structure of Interrupt request register 2 .................................................................... 44 2.4.9 Structure of Interrupt control register 2 ..................................................................... 44 2.4.10 Serial I/O connection examples (1) .......................................................................... 45 2.4.11 Serial I/O connection examples (2) .......................................................................... 46 2.4.12 Serial I/O transfer data format .................................................................................. 47 2.4.13 Connection diagram .................................................................................................... 48 2.4.14 Timing chart ................................................................................................................. 48 2.4.15 Registers setting related to transmitting side ......................................................... 49 2.4.16 Registers setting related to receiving side .............................................................. 50 2.4.17 Control procedure of transmitting side ..................................................................... 51 2.4.18 Control procedure of receiving side ......................................................................... 52 2.4.19 Connection diagram .................................................................................................... 53 2.4.20 Timing chart ................................................................................................................. 53 2.4.22 Setting of serial I/O transmission data .................................................................... 54 2.4.21 Registers setting related to Serial I/O ..................................................................... 54 2.4.23 Control procedure of Serial I/O ................................................................................. 55 2.4.24 Connection diagram .................................................................................................... 56 2.4.25 Timing chart ................................................................................................................. 57 2.4.26 Related registers setting ............................................................................................ 57 2.4.27 Control procedure of master unit .............................................................................. 58 2.4.28 Control procedure of slave unit ................................................................................ 59 2.4.29 Connection diagram (Communication using UART) ............................................... 60 2.4.30 Timing chart (using UART) ........................................................................................ 60 2.4.31 Registers setting related to transmitting side ......................................................... 62 2.4.32 Registers setting related to receiving side .............................................................. 63 2.4.33 Control procedure of transmitting side ..................................................................... 64 2.4.34 Control procedure of receiving side ......................................................................... 65 2.4.35 Sequence of setting serial I/O control register again ............................................ 67 2.7.1 Memory map of registers related to A/D converter .................................................. 71 2.7.2 Structure of AD control register .................................................................................. 71 2.7.3 Structure of AD conversion register 1 ....................................................................... 72 2.7.4 Structure of AD conversion register 2 ....................................................................... 72 2.7.5 Structure of Interrupt request register 2 .................................................................... 73 2.7.6 Structure of Interrupt control register 2 ..................................................................... 73 2.7.7 Connection diagram ...................................................................................................... 74 2.7.8 Related registers setting .............................................................................................. 74 2.7.9 Control procedure for 8-bit read ................................................................................. 75 2.7.10 Control procedure for 10-bit read ............................................................................. 75 2.8.1 Memory map of registers related to watchdog timer ............................................... 77 2.8.2 Structure of Watchdog timer control register ............................................................ 77 2.8.3 Structure of CPU mode register ................................................................................. 78 2.8.4 Watchdog timer connection and division ratio setting ............................................. 79 2.8.5 Related registers setting .............................................................................................. 80 2.8.6 Control procedure .......................................................................................................... 80 2.9.1 Example of poweron reset circuit ............................................................................... 81 2.9.2 RAM backup system ..................................................................................................... 81 2.10.1 Memory map of registers related to PLL ................................................................. 83 2.10.2 Structure of USB control register ............................................................................. 83 2.10.3 Structure of CPU mode register ............................................................................... 84 2.10.4 Structure of PLL control register .............................................................................. 84 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 8 of 13 List of figures 38K0 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.10.5 Block diagram for frequency synthesizer circuit ..................................................... 85 2.10.6 Related registers setting when hardware reset ...................................................... 86 2.10.7 Related registers setting when stop mode .............................................................. 87 2.10.8 Related registers setting when recovery from stop mode .................................... 88 2.11.1 Memory map of registers related to clock generating circuit ............................... 89 2.11.2 Structure of USB control register ............................................................................. 89 2.11.3 Structure of CPU mode register ............................................................................... 90 2.11.4 Structure of PLL control register .............................................................................. 90 2.11.5 Related registers setting ............................................................................................ 91 2.11.6 Related registers setting ............................................................................................ 93 2.12.1 Memory map of registers related to standby function ........................................... 94 2.12.2 Structure of MISRG .................................................................................................... 94 2.12.3 Oscillation stabilizing time at restoration by reset input ....................................... 96 2.12.4 Execution sequence example at restoration by occurrence of INT0 interrupt request ...................................................................................................................................... 98 2.12.5 Reset input time ........................................................................................................ 100 2.13.1 Memory map of flash memory version for 38K0 Group ...................................... 102 2.13.2 Memory map of registers related to flash memory .............................................. 103 2.13.3 Structure of Flash memory control register ........................................................... 103 2.13.4 Rewrite example of built-in flash memory in standard serial I/O mode ............ 106 2.13.5 Connection example in standard serial I/O mode (1) .......................................... 107 2.13.6 Connection example in standard serial I/O mode (2) .......................................... 107 2.13.7 Connection example in standard serial I/O mode (3) .......................................... 108 2.13.8 Example of rewrite system for built-in flash memory in CPU rewrite mode .... 109 2.13.9 CPU rewrite mode beginning/release flowchart .................................................... 110 CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 Output switching characteristics measurement circuit ............................................. 11 3.1.2 USB output switching characteristics measurement circuit (1) for D0- ................. 13 3.1.3 USB output switching characteristics measurement circuit (2) for D0+ ................ 13 3.1.4 Timing chart (1) ............................................................................................................. 14 3.1.5 Timing chart (2) ............................................................................................................. 15 3.1.6 Timing chart (3) ............................................................................................................. 16 3.1.7 Timing chart (4) ............................................................................................................. 17 3.1.8 Timing chart (5) ............................................................................................................. 18 3.1.9 Timing chart (6) ............................................................................................................. 19 3.2.1 Sequence of changing relevant register .................................................................... 22 3.2.2 Sequence of check of interrupt request bit ............................................................... 23 3.2.3 Sequence of setting serial I/O control register again .............................................. 25 3.2.4 Initialization of processor status register ................................................................... 29 3.2.5 Sequence of PLP instruction execution ..................................................................... 29 3.2.6 Stack memory contents after PHP instruction execution ........................................ 29 3.2.7 Status flag at decimal calculations ............................................................................. 30 3.3.1 Selection of packages .................................................................................................. 32 3.3.3 Wiring for clock I/O pins .............................................................................................. 33 3.3.4 Wiring for CNVSS pin ..................................................................................................... 33 3.3.5 Wiring for the VPP pin of the flash memory version ................................................. 34 3.3.6 Bypass capacitor across the VSS line and the VCC line ........................................... 34 3.3.7 Analog signal line and a resistor and a capacitor ................................................... 35 3.3.8 Wiring for ___________ current signal line ......................................................................... 36 a large 3.3.9 Wiring of RESET pin .................................................................................................... 36 3.3.10 VSS pattern on the underside of an oscillator ......................................................... 37 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 9 of 13 List of figures 38K0 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.3.11 Setup for I/O ports ...................................................................................................... 37 3.3.12 Watchdog timer by software ...................................................................................... 38 3.4.1 Structure of Port Pi ....................................................................................................... 39 3.4.2 Structure of Port Pi direction register ........................................................................ 39 3.4.3 Structure of USB control register ................................................................................ 40 3.4.4 Structure of USB function enable register ................................................................. 40 3.4.5 Structure of USB function address register ............................................................... 40 3.4.6 Structure of Frame number register Low ................................................................... 41 3.4.7 Structure of Frame number register High .................................................................. 41 3.4.8 Structure of USB interrupt source enable register ................................................... 41 3.4.9 Structure of USB interrupt source register ................................................................ 42 3.4.10 Structure of Endpoint index register ......................................................................... 42 3.4.11 Structure of EP00 stage register .............................................................................. 43 3.4.12 Structure of EP01 set register .................................................................................. 43 3.4.13 Structure of EP02 set register .................................................................................. 44 3.4.14 Structure of EP03 set register .................................................................................. 44 3.4.15 Structure of EP00 control register 1 ........................................................................ 45 3.4.16 Structure of EP01 control register 1 ........................................................................ 45 3.4.17 Structure of EP02 control register 1 ........................................................................ 45 3.4.18 Structure of EP03 control register 1 ........................................................................ 46 3.4.19 Structure of EP00 control register 2 ........................................................................ 46 3.4.20 Structure of EP01 control register 2 ........................................................................ 46 3.4.21 Structure of EP02 control register 2 ........................................................................ 47 3.4.22 Structure of EP03 control register 2 ........................................................................ 47 3.4.23 Structure of EP00 control register 3 ........................................................................ 47 3.4.24 Structure of EP01 control register 3 ........................................................................ 48 3.4.25 Structure of EP02 control register 3 ........................................................................ 48 3.4.26 Structure of EP03 control register 3 ........................................................................ 48 3.4.27 Structure of EP00 interrupt source register ............................................................ 49 3.4.28 Structure of EP01 interrupt source register ............................................................ 50 3.4.29 Structure of EP02 interrupt source register ............................................................ 50 3.4.30 Structure of EP03 interrupt source register ............................................................ 51 3.4.31 Structure of EP00 byte number register .................................................................. 51 3.4.32 Structure of EP01 byte number register 0 .............................................................. 51 3.4.33 Structure of EP02 byte number register 0 .............................................................. 52 3.4.34 Structure of EP03 byte number register 0 .............................................................. 52 3.4.35 Structure of EP01 byte number register 1 .............................................................. 52 3.4.36 Structure of EP02 byte number register 1 .............................................................. 53 3.4.37 Structure of EP03 byte number register 1 .............................................................. 53 3.4.38 Structure of Prescaler12, Prescaler X ..................................................................... 53 3.4.39 Structure of Timer 1 ................................................................................................... 54 3.4.40 Structure of Timer 2, Timer X ................................................................................... 54 3.4.41 Structure of Timer X mode register ......................................................................... 55 3.4.42 Structure of Transmit/Receive buffer register ......................................................... 55 3.4.43 Structure of Serial I/O status register ...................................................................... 56 3.4.44 Structure of EXB interrupt source enable register ............................................... 56 3.4.45 Structure of EXB interrupt source register .............................................................. 57 3.4.46 Structure of EXB index register ................................................................................ 57 3.4.47 Structure of Register window 1 ................................................................................. 58 3.4.48 Index00[low]; Structure of External I/O configuration register ............................ 58 3.4.49 Index01[low]; Structure of Transmit/Receive buffer register ................................. 59 3.4.50 Index02[low]; Structure of Memory channel operation mode register ................. 59 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 10 of 13 List of figures 38K0 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.4.51 3.4.52 3.4.53 3.4.54 3.4.55 3.4.56 3.4.57 3.4.58 3.4.59 3.4.60 3.4.61 3.4.62 3.4.63 3.4.64 3.4.65 3.4.66 3.4.67 3.4.68 3.4.69 3.4.70 3.4.71 3.4.72 3.4.73 3.4.74 3.4.75 3.4.76 3.4.77 3.4.78 3.4.79 3.4.80 3.4.81 Index03[low]; Structure of Memory address counter .............................................. 59 Index04[low]; Structure of End address register .................................................... 60 Structure of Register window 2 ................................................................................. 60 Index00[high]; Structure of External I/O configuration register ........................... 60 Index03[high]; Structure of Memory address counter ............................................ 61 Index04[high]; Structure of End address register ................................................... 61 Structure of AD control register ................................................................................ 61 Structure of AD conversion register 1 ..................................................................... 62 Structure of AD conversion register 2 ..................................................................... 62 Structure of Watchdog timer control register .......................................................... 63 Structure of CPU mode register ............................................................................... 63 Structure of Interrupt request register 1 .................................................................. 64 Structure of Interrupt request register 2 .................................................................. 64 Structure of Interrupt control register 1 ................................................................... 65 Structure of Interrupt control register 2 ................................................................... 65 Structure of Serial I/O control register ..................................................................... 66 Structure of UART control register ........................................................................... 66 Structure of Baud rate generator .............................................................................. 67 Structure of EP01 MAX. packet size register ......................................................... 67 Structure of EP02 MAX. packet size register ......................................................... 67 Structure of EP03 MAX. packet size register ......................................................... 68 Structure of EP00 buffer area set register .............................................................. 68 Structure of EP01 buffer area set register .............................................................. 68 Structure of EP02 buffer area set register .............................................................. 69 Structure of EP03 buffer area set register .............................................................. 69 Structure of Port P0 pull-up control register ........................................................... 70 Structure of Port P5 pull-up control register ........................................................... 70 Structure of Interrupt edge selection register ......................................................... 71 Structure of PLL control register .............................................................................. 71 Structure of MISRG .................................................................................................... 72 Structure of Flash memory control register ............................................................. 72 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 11 of 13 List of tables 38K0 Group List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description ................................................................................................................... 4 2 List of 38K0 group products (L version) ....................................................................... 6 3 Push and pop instructions of accumulator or processor status register .................. 8 4 Set and clear instructions of each bit of processor status register .......................... 9 5 I/O ports functions .......................................................................................................... 13 6 Interrupt vector addresses and priority ........................................................................ 17 7 USB interrupt sources .................................................................................................... 30 8 Summary of 38K0 group's flash memory version ...................................................... 82 9 List of software commands (CPU rewrite mode) ....................................................... 87 10 Definition of each bit in status register ..................................................................... 89 11 Description of pin function (Standard Serial I/O Mode) .......................................... 95 12 Software commands (Standard serial I/O mode) ..................................................... 97 13 Status register (SRD) ................................................................................................. 104 14 Status register 1 (SRD1) ........................................................................................... 104 15 Relative formula for a reference voltage VREF of A/D converter and Vref ...... 111 16 Change of AD conversion register during A/D conversion ................................... 111 CHAPTER 2 APPLICATION 2.1.1 Handling of unused pins ............................................................................................. 5 2.2.1 Interrupt sources, vector addresses and priority of 38K0 group ......................... 11 2.2.2 List of interrupt bits according to interrupt source ................................................ 16 2.3.1 CNTR0 active edge selection bit function ............................................................... 25 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values . 61 2.10.1 PLL operation mode selection bits setting example ........................................... 85 2.10.2 USB clock division ratio selection bits setting example ..................................... 86 2.11.1 Example of internal clock f(f) generation using main clock f(XIN) ..................... 91 2.11.2 Example of internal clock f(f) generation using fSYN ........................................ 92 2.12.1 State in stop mode .................................................................................................. 95 2.12.2 State in wait mode ................................................................................................... 99 2.13.1 Setting of programmers when parallel programming ........................................ 104 2.13.2 Connection example to flash programmer when serial programming (4 wires) .. ................................................................................................................................ 104 Table 2.13.3 Setting condition in serial I/O mode .................................................................. 106 Table Table Table Table Table Table Table Table Table Table Table Table Table Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 12 of 13 List of tables 38K0 Group CHAPTER 3 APPENDIX Table 3.1.1 Absolute maximum ratings .......................................................................................... 2 Table 3.1.2 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) ............................................................................ 3 Table 3.1.3 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) ............................................................................ 4 Table 3.1.4 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) ............................................................................................ 5 Table 3.1.5 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) ............................................................................................ 6 Table 3.1.6 AD Converter characteristics (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) ............................................................................................ 7 Table 3.1.7 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) ......................................................................................................... 8 Table 3.1.8 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) ......................................................................................................... 8 Table 3.1.9 Timing requirements of external bus interface (EXB) (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) ............................................ 9 Table 3.1.10 Timing requirements of external bus interface (EXB) (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) .......................................... 10 Table 3.1.11 Switching characteristics (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) .......................................................................................... 11 Table 3.1.12 Switching characteristics (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) .......................................................................................... 11 Table 3.1.13 Switching characteristics of external bus interface (EXB) (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) .............................. 12 Table 3.1.14 Switching characteristics of external bus interface (EXB) (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) .............................. 12 Table 3.1.15 Switching characteristics (USB ports) (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) ........................................................................ 13 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 13 of 13 CHAPTER 1 HARDWARE DESCRIPTION FEATURES PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS FUNCTIONAL DESCRIPTION SUPPLEMENT HARDWARE 38K0 Group DESCRIPTION/FEATURES/PIN CONFIGURATION DESCRIPTION The 38K0 group is the 8-bit microcomputer based on the 740 family core technology. The 38K0 group has the USB function, an 8-bit bus interface, a Serial Interface, three 8-bit timers, and an 8-channel 10-bit A/D converter, which are available for the PC peripheral I/O device. The various microcomputers in the 38K0 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. * Timers ............................................................................. 8-bit 3 *Watchdog timer ............................................................. 16-bit 1 * Serial Interface Serial I/O (UART or Clock-synchronized) ...................... 8-bit 1 A/D converter ................................................ 10-bit 8 channels (8-bit reading available) LED direct drive port ................................................................... 4 Clock generating circuit (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage (L version) System clock/Internal clock division mode At 12 MHz/2-divide mode( = 6 MHz) ................... 4.00 to 5.25 V At 8 MHz/Through mode ( = 8 MHz) ................... 4.00 to 5.25 V At 6 MHz/Through mode ( = 6 MHz) ................... 3.00 to 5.25 V Power dissipation At 5 V power source voltage .................................. 125 mW (typ.) (at 8 MHz system clock, in through mode) At 3.3 V power source voltage ................................ 30 mW (typ.) (at 6 MHz system clock, in through mode) Operating temperature range .................................... -20 to 85C Packages FP ............................ PLQP0064GA-A (64-pin 14 14 mm LQFP) HP ............................ PLQP0064KB-A (64-pin 10 10 mm LQFP) * * * * FEATURES * Basic machine-language instructions ....................................... 71 * The minimum instruction execution time .......................... 0.25 s System clock: (at 8 MHz system clock) Reference frequency to internal circuit except USB function * * Memory size * * * * * ROM ................................................................ 16 K to 32 K bytes RAM ............................................................... 1024 to 2048 bytes Programmable input/output ports ............................................. 48 Software pull-up resistors Interrupts .................................................. 15 sources, 15 vectors USB function (Full-Speed USB2.0 specification) ...... 4 endpoints External bus interface ....................................... 8-bit 1 channel * * 47 46 45 44 43 42 41 48 P06 P07 P40/EXDREQ/RXD P41/EXDACK/TXD P42/EXTC/SCLK P43/EXA1/SRDY P30 P31 P32 P33/EXINT P34/EXCS P35/EXWR P36/EXRD P37/EXA0 P10/DQ0/AN0 P11/DQ1/AN1 40 39 38 37 36 35 34 33 P05 P04 P03 P02 P01 P00 P57 P56 P55 P54 P53 P52/INT1 P51/CNTR0 P50/INT0 P27 P26 PIN CONFIGURATION (TOP VIEW) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 M38K07M4L-XXXFP/HP M38K09F8LFP/HP P25 P24 P23 P22 P21 P20 D0D0+ TrON USBVREF DVCC PVCC PVSS P63(LED3) P62(LED2) P61(LED1) 10 11 12 13 14 P12/DQ2/AN2 P13/DQ3/AN3 P14/DQ4/AN4 P15/DQ5/AN5 P16/DQ6/AN6 P17/DQ7/AN7 CNVSS RESET VCCE VREF VSS XIN XOUT 15 Package type : PLQP0064GA-A (64P6U-A)/PLQP0064KB-A (64P6Q-A) Fig. 1 Pin configuration of 38K0 group Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 2 of 112 P60(LED0) VCC CNVSS2 16 2 3 4 5 6 7 8 1 9 38K0 Group FUNCTIONAL BLOCK DIAGRAM (Package : PLQP0064GA-A/PLQP0064KB-A) PVSS PVCC XIN XOUT VCCE VSS VCC RESET CNVSS CNVSS2 15 7 8 14 11 9 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 20 21 12 13 FUNCTIONAL BLOCK Fig. 2 Functional block diagram Data bus page 3 of 112 Clock generating circuit RAM ROM CPU Timer 1 (8) Timer 2 (8) Timer X (8) RAM I/F Watchdog timer CNTR0 INT1 INT0 SI/O EXTBUS (8) USB 10-bit A/D converter (8) P6 (4) P3 (8) P5 (8) P4 (4) P2 (8) P1 (8) P0(8) 16 17 18 19 51 52 53 54 35 36 37 38 39 40 41 42 55 56 57 58 59 60 61 62 22 23 24 25 26 27 28 29 30 31 32 33 34 10 63 64 1 2 3 4 5 6 43 44 45 46 47 48 49 50 FUNCTIONAL BLOCK DVCC TrON D0USBVREF D0+ VREF HARDWARE HARDWARE 38K0 Group PIN DESCRIPTION PIN DESCRIPTION Table 1. Pin description Pin VCC, VSS VCCE CNVSS CNVSS2 VREF DVCC PVCC, PVSS RESET XIN XOUT USBVREF Name Power source Analog power source CNVSS CNVSS2 Analog reference voltage input Analog power source Reset input Clock input Clock output USB reference power source Function Function except a port function * Apply voltage of 3.0 V - 5.25 V (L version) to VCC, and 0 V to VSS. * Power source pin for ports P1, P3, P4 and analog circuit. Connect this pin to VCC. * This pin controls the operation mode of the chip. Connect this pin to VSS. In the flash memory mode, this pin becoems VPP power source input pin. * This pin controls the operation mode of the chip. Connect this pin to VSS. * Reference voltage input pin for A/D converter. * Power source pin for analog circuit. * Connect the DVCC and PVCC pins to VCC, and the PVSS pin to VSS. * Reset input pin for active "L" * Input and output pins for the main clock generating circuit. * Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * Power source pin for USB port circuit. In Vcc = 4.00 to 5.25 V use the built-in USB reference voltage circuit. In Vcc = 3.60 to 4.00 V apply 3.3 V power supply from the external because use of the built-in USB reference voltage circuit is prohibited in this voltage range. In Vcc = 3.00 to 3.60 V connect this pin to VCC because use of the built-in USB reference voltage circuit is prohibited in this voltage range. * Output pin to pull-up D0+ by 1.5 k external resistor. * USB upstream I/O port * USB input level * USB output level output structure * 8-bit I/O port * Key input pins (key-on wake up interrupt) * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level * CMOS 3-state output structure * Pull-up control is enabled. * 8-bit I/O port * A/D converter input pins * I/O direction register allows each pin to be individually * External bus interface function pins programmed as either input or output. * CMOS compatible input level * CMOS 3-state output structure * 8-bit I/O port * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level * CMOS 3-state output structure * 8-bit I/O port * I/O direction register allows each pin to be individually * External bus interface function pins programmed as either input or output. * CMOS compatible input level * CMOS 3-state output structure * 4-bit I/O port * Serial I/O function pins * I/O direction register allows each pin to be individually * External bus interface function pins programmed as either input or output. * CMOS compatible input level * CMOS 3-state output structure * 8-bit I/O port * Interrupt input pin * I/O direction register allows each pin to be individually * Timer X funciton pin programmed as either input or output. * Interrupt input pin * CMOS compatible input level * CMOS 3-state output structure * 4-bit I/O port * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level * CMOS 3-state output structure * Output large current for LED drive is enabled. TrON D0+, D0- USB reference voltage output USB upstream I/O I/O port P0 P00-P07 P10/DQ0/AN0- I/O port P1 P17/DQ7/AN7 P20-P27 I/O port P2 P30-P32 I/O port P3 P33/ExINT P34/ExCS P35/ExWR P36/ExRD P37/ExA0 P40/ExDREQ/RxD I/O port P4 P41/ExDACK/TxD P42/ExTC/SCLK P43/ExA1/SRDY P50/INT0 P51/CNTR0 P52/INT1 P53-P57 P60-P63 I/O port P5 I/O port P6 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 4 of 112 HARDWARE 38K0 Group PART NUMBERING PART NUMBERING Product M38K0 7 M 4 - XXX FP Package type FP : PLQP0064GA-A package HP : PLQP0064KB-A package ROM number Omitted in the flash memory version. - : Standard Omitted in the flash memory version. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user's ROM area. However, they can be programmed or erased in the flash memory version, so that users can use them. Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 3 Part numbering Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 5 of 112 HARDWARE 38K0 Group GROUP EXPANSION GROUP EXPANSION Mitsubishi plans to expand the 38K0 group as follows. Packages PLQP0064GA-A ...................... 0.8 mm-pitch plastic molded LQFP PLQP0064KB-A ....................... 0.5 mm-pitch plastic molded LQFP 100D0M ........................... 0.65 mm-pitch metal seal PIGGY BACK Memory Type Support for mask ROM and flash memory versions. Memory Size Flash memory size .......................................................... 32 Kbytes Mask ROM size ............................................................... 16 Kbytes RAM size .......................................................... 1024 to 2048 bytes Memory Expansion Plan ROM size (bytes) : Mass Production 60K 32K M38K09F8L 16K M38K07M4L 8K 256 512 1,024 RAM size (bytes) 2,048 Fig. 4 Memory expansion plan Currently products are listed below. Table 2. List of 38K0 group products (L version) Product M38K07M4L-XXXFP M38K07M4L-XXXHP M38K09F8LFP M38K09F8LHP M38K09RFS ROM size (bytes) ROM size for User in ( ) 16384 (16254) 32768 (32638) -- RAM size (bytes) 1024 2048 2048 Package PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A 100D0M As of October 2006 Remarks Mask ROM version Flash memory version Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 6 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 38K0 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. The CPU has the 6 registers. The register structure is shown in Figure 5. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". Figure 6 shows the store and the return movement into the stack. If there are registers other than those described in Figure 5, the users need to store them with the program. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 5 740 Family CPU register structure Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 7 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt enable flag is "1" Interrupt disable flag is "0" Fig. 6 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 8 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC *Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 9 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16. b7 b0 0 1 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0: Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns "1" when read) (Do not write "0" to this bit) Not used (returns "0" when read) (Do not write "1" to this bit) System clock selection bit 0 : Main clock (XIN) 1 : fSYN System clock division ratio selection bits b7 b6 0 0 : = f(system clock)/8 (8-divide mode) 0 1 : = f(system clock)/4 (4-divide mode) 1 0 : = f(system clock)/2 (2-divide mode) 1 1 : = f(system clock) (Through mode) Fig. 7 Structure of CPU mode register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 10 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. In the flash memory version, program and erase can be performed in the reserved area. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFFE16 Reserved ROM area FFFF16 Interrupt vector area Special page ROM FF0016 FFDC16 ZZZZ16 YYYY16 Reserved ROM area (128 bytes) Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 0FE016 0FFF16 SFR area Not used XXXX16 RAM 010016 000016 SFR area 004016 Zero page Fig. 8 Memory map diagram Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 11 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Reserved (Note) 000F16 Reserved (Note) 001016 USB control register (USBCON) 001116 USB function enable register (USBAE) 001216 USB function address register (USBA0) 001316 Reserved (Note) 001416 Frame number register Low (FNUML) 001516 Frame number register High (FNUMH) 001616 USB interrupt source enable register (USBICON) 001716 USB interrupt source register (USBIREQ) 001816 Endpoint index register (USBINDEX) 001916 Endpoint field register 1 (EPXXREG1) 001A16 Endpoint field register 2 (EPXXREG2) 001B16 Endpoint field register 3 (EPXXREG3) 001C16 Endpoint field register 4 (EPXXREG4) 001D16 Endpoint field register 5 (EPXXREG5) 001E16 Endpoint field register 6 (EPXXREG6) 001F16 Endpoint field register 7 (EPXXREG7) 002016 Prescaler 12 (PRE12) 002116 Timer 1 (T1) 002216 Timer 2 (T2) 002316 Timer X mode register (TM) 002416 Prescaler X (PREX) 002516 Timer X (TX) 002616 Transmit/Receive buffer register (TB/RB) 002716 Serial I/O status register (SIOSTS) 002816 Reserved (Note) 002916 Reserved (Note) 002A16 Reserved (Note) 002B16 Reserved (Note) 002C16 Reserved (Note) 002D16 Reserved (Note) 002E16 Reserved (Note) 002F16 Reserved (Note) 003016 EXB interrupt source enable register (EXBICON) 003116 EXB interrupt source register (EXBIREQ) 003216 Reserved (Note) 003316 EXB index register (EXBINDEX) 003416 EXB field register 1 (EXBREG1) 003516 EXB field register 2 (EXBREG2) 003616 AD control register (ADCON) 003716 AD conversion register 1 (AD1) 003816 AD conversion register 2 (AD2) 003916 Watchdog timer control register (WDTCON) 003A16 Reserved (Note) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F16 Interrupt control register 2(ICON2) 0FE016 Serial I/O control register (SIOCON) 0F E116 UART control register (UARTCON) 0FE216 Baud rate generator (BRG) 0F E316 Reserved (Note) 0F E416 Reserved (Note) 0FE516 Reserved 0F E616 Reserved 0F E716 Reserved 0FE816 Reserved 0F E916 Reserved (Note) (Note) (Note) (Note) 0FF016 Port P0 pull-up control register (PULL0) 0FF116 Reserved (Note) 0FF216 Port P5 pull-up control register (PULL5) 0FF316 0FF416 0FF516 0FF616 Interrupt edge selection register (INTEDGE) Reserved (Note) Reserved (Note) Reserved (Note) (Note) 0FEA16 Reserved (Note) 0FEB16 Reserved (Note) 0FEC16 Endpoint field register 8 (EPXXREG8) 0FED16 Endpoint field register 9 (EPXXREG9) 0FEE16 Reserved (Note) 0FEF16 Reserved (Note) 0FF716 Reserved (Note) 0FF816 PLL control register (PLLCON) 0FF916 Reserved (Note) 0FFA16 Reserved (Note) 0FFB16 MISRG 0FF C16 Reserved (Note) 0FF D16 Reserved (Note) 0FFE16 Flash memory control register (FMCR) 0F FF16 Reserved (Note) Note: Do not write any data to these addresses, because these areas are reserved. Fig. 9 Memory map of special function register (SFR) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 12 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 5 I/O ports functions Pin P00-P07 Name Port P0 Input/Output Input/output, individual bits I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output (Power source is VCCE) CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output (Power source is VccE) Non-Port Function Key-on wake up Related SFRs Port P0 pull-up control register AD control register EXB control register Diagram No. (1) P10-P17 Port P1 A/D conversion input External bus interface funciton I/O (2) P20-P27 Port P2 (3) P30-P32 P33/ExINT P34/ExCS P35/ExWR P36/ExRD P37/ExA0 P40/RxD/ ExDREQ P41/TxD/ ExDACK P42/SCLK/ ExTC P43/SRDY/ ExA1 P50/INT0 P52/INT1 Port P3 External bus interface funciton output External bus interface funciton input EXB control register EXB control register (4) (5) (6) Port P4 Port P5 CMOS compatible input level CMOS 3-state output Serial I/O input External bus interface funciton output Serial I/O output External bus interface funciton input Serial I/O I/O External bus interface funciton input Serial I/O output External bus interface funciton input External interrupt input P51/CNTR0 P53-P57 P60-P63 Timer X function I/O Port P6 Serial I/O control register EXB control register Serial I/O control register EXB control register Serial I/O control register EXB control register Serial I/O control register EXB control register Port P5 pull-up control register Interrupt edge selection register Timer X mode register (7) (8) (9) (10) (11) (12) (13) (14) Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 13 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (1) Port P0 Pull-up control bit (4) Ports P30-P32 VCCE Direction register Direction register Data bus Port latch Data bus Port latch Key-on wake-up input (2) Port P1 EXOE External bus interface enable bit Direction register (5) Port P33 VCCE External bus interface enable bit Direction register VCCE Data bus Data bus Port latch Port latch EXINT output EXB data output EXB data input Output buffer Input buffer (6) Ports P34, P35, P36, P37 VCCE External bus interface enable bit A/D conversion input Analog input pin selection bit Data bus Port latch Direction register (3) Port P2 Direction register Data bus Port latch EXCS(P34) EXWR(P35) EXRD(P36) EXA0(P37) External bus interface enable bit Fig. 10 Port block diagram (1) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 14 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (7) Port P40 Serial I/O enable bit Receive enable bit External bus interface enable bit Direction register (11) Ports P50, P52 Pull-up control bit VCCE Direction register Data bus Port latch Data bus Port latch INT0 (P50), INT1 (P52) interrupt input EXDreq output Serial I/O input (8) Port P41 Serial I/O enable bit Receive enable bit External bus interface enable bit Direction register (12) Port P51 VCCE Direction register Data bus Port latch Data bus Port latch Pulse output mode Serial I/O output EXDack External bus interface enable bit Timer output CNTR0 interrupt input (9) Port P42 Serial I/O enable bit Serial I/O mode selection bit Serial I/O synchronous clock selection bit Serial I/O enable bit External bus interface enable bit Direction register (13) Ports P53-P57 VCCE Direction register Data bus Port latch Data bus Port latch Serial I/O clock output Serial I/O external clock input (14) Port P6 EXTC Serial I/O synchronous clock selection bit External bus interface enable bit Data bus Direction register (10) Port P43 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit External bus interface enable bit Direction register Port latch VCCE Data bus Port latch Serial I/O output EXA1 External bus interface enable bit Fig. 11 Port block diagram (2) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 15 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 Port P0 pull-up control register (PULL0 : address 0FF016) P00 pull-up control bit 0 : No pull-up 1 : Pull-up P01 pull-up control bit 0 : No pull-up 1 : Pull-up P02 pull-up control bit 0 : No pull-up 1 : Pull-up P03 pull-up control bit 0 : No pull-up 1 : Pull-up P04 pull-up control bit 0 : No pull-up 1 : Pull-up P05 pull-up control bit 0 : No pull-up 1 : Pull-up P06 pull-up control bit 0 : No pull-up 1 : Pull-up P07 pull-up control bit 0 : No pull-up 1 : Pull-up b7 b0 Port P5 pull-up control register (PULL5 : address 0FF216) P50 pull-up control bit 0 : No pull-up 1 : Pull-up Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0". P52 pull-up control bit 0 : No pull-up 1 : Pull-up Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". Fig. 12 Structure of port I/O-related registers Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 16 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION INTERRUPTS Interrupts occur by fifteen sources: four external, ten internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. sNotes on interrupts When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 0FF316), Timer X mode register (address 002316) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit). Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Table 6 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) USB bus reset USB SOF USB device External bus INT0 Timer X Timer 1 Timer 2 INT1 (Note 3) Serial I/O reception Serial I/O transmission CNTR0 Key-on wake up A/D conversion BRK instruction Priority 1 2 3 4 5 6 7 8 9 10 -- 11 12 13 14 15 16 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 Interrupt Request Generating Conditions At reset At detection of USB bus reset signal (2.5 s interval SE0) At detection of USB SOF signal At detection of resume signal (K state or SE0) or suspend signal (3 ms interval bus idle), or at completion of transaction At completion of reception or transmission or at completion of DMA transmission At detection of either rising or falling edge of INT0 input At timer X underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of INT1 input (Note 4) At completion of serial I/O data reception At completion of serial I/O data transmission At detection of either rising or falling edge of CNTR0 input At falling of conjunction of input level for port P0 (at input mode) At completion of A/D conversion At BRK instruction execution Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Nothing is arranged in these vector addresses. 4: Fix bit 1 of interrupt control register 2 (address 003F16) to "0". Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 17 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 0FF316) INT0 interrupt edge selection bit Not used (return "0" when read) INT1 interrupt edge selection bit Not used (return "0" when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) USB bus reset interrupt request bit USB SOF interrupt request bit USB device interrupt request bit EXB interrupt request bit INT0 interrupt request bit Timer X interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) USB bus reset interrupt enable bit USB SOF interrupt enable bit USB device interrupt enable bit EXB interrupt enable bit INT0 interrupt enable bit Timer X interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled "0" can be set by software, but "1" cannot be set. b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) INT1 interrupt request bit Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0". Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit CNT R0 interrupt request bit Key-on wake-up interrupt request bit A/D conversion interrupt request bit Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0". 0 : No interrupt request issued 1 : Interrupt request issued "0" can be set by software, but "1" cannot be set. b7 b0 Interrupt control register 2 (ICON2 : address 003F16) INT1 interrupt enable bit Fix this bit to "0". Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit CNT R0 interrupt enable bit Key-on wake-up interrupt enable bit A/D conversion interrupt enable bit Fix this bit to "0". 0 : Interrupts disabled 1 : Interrupts enabled Fig. 14 Structure of interrupt-related registers Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 18 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Key Input Interrupt (Key-on Wake Up) A Key-on wake up interrupt request is generated by applying a falling edge to any pin of port P0 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 15, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P00-P03. Port PXx "L" level output PULL 0 register Bit 7 = "0" Port P07 direction register = "1" Port P07 latch Key input interrupt request P07 output PULL 0 register Bit 6 = "0" Port P06 direction register = "1" Port P06 latch P06 output PULL 0 register Bit 5 = "0" Port P05 direction register = "1" Port P05 latch P05 output PULL 0 register Bit 4 = "0" Port P04 direction register = "1" Port P04 latch P04 output PULL 0 register Bit 3 = "1" Port P03 direction register = "0" Port P03 latch Port P0 Input reading circuit P03 input PULL 0 register Bit 2 = "1" Port P02 direction register = "0" Port P02 latch P02 input PULL 0 register Bit 1 = "1" Port P01 direction register = "0" P01 input Port P01 latch PULL 0 register Bit 0 = "1" Port P00 direction register = "0" Port P00 latch P00 input P-channel transistor for pull-up CMOS output buffer Fig. 15 Connection example when using key input interrupt and port P0 block diagram Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 19 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION TIMERS The 38K0 group has three timers: timer X, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down count timers. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". Timer 1 and Timer 2 The count source of prescaler 12 is the system clock divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow periodically sets the interrupt request bit. Timer X Timer X can each select in one of four operating modes by setting the timer X mode register. (1) Timer Mode b7 b0 Timer X mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNT R0 active edge switch bit 0 : Falling edge active for CNTR0 interrupt Count at rising edge in event counter mode 1 : Rising edge active for CNTR0 interrupt Count at falling edge in event counter mode Timer X count stop bit 0 : Count start 1 : Count stop Not used (return "0" when read) The timer counts the count source selected by timer count source selection bit. (2) Pulse Output Mode The timer counts the system clock divided by 16. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 pin is inverted. If the CNTR0 active edge selection bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P51 direction register to output mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 pin. When the CNTR0 active edge selection bit is "0", the rising edge of the CNTR0 pin is counted. When the CNTR0 active edge selection bit is "1", the falling edge of the CNTR0 pin is counted. Fig. 16 Structure of timer X mode register (4) Pulse Width Measurement Mode If the CNTR0 active edge selection bit is "0", the timer counts the system clock divided by 16 while the CNTR0 pin is at "H". If the CNTR0 active edge selection bit is "1", the timer counts it while the CNTR0 pin is at "L". The count can be stopped by setting "1" to the timer X count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 20 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Data bus Divider System clock 1/16 Pulse width m easurem ent mode Prescaler X latch (8) Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge selection bit "0" "1" CNTR0 active edge selection bit "1" Q Q Toggle flip-flop R T Timer X latch write Pulse output mode Event counter mode Timer X count stop bit CNTR0 interrupt request bit Timer X latch (8) Timer X (8) Timer X interrupt request bit P51/CNTR0 Port P51 direction register Port P51 latch Pulse output mode "0" Data bus Prescaler 12 latch (8) Divider System clock 1/16 Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) Timer 2 interrupt request bit Timer 1 interrupt request bit Fig. 17 Timer block diagram Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 21 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION SERIAL INTERFACE SERIAL I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register (bit 6 of address 0FE016) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the Trancemit/Receive buffer register. Data bus Address 002616 Receive buffer register Serial I/O control register Address 0FE016 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P40/EXDREQ/RxD Receive shift register Shift clock P42/EXTC/SCLK Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator BRG count source selection bit System clock 1/4 P43/EXA1/SRDY F/F Falling-edge detector 1/4 Address 0FE216 Clock control circuit Shift clock P41/EXDACK/TxD Transmit shift register Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 002716 Address 002616 Data bus Serial I/O status register Fig. 18 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD Serial input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY Write signal to receive/transmit buffer register (address 002616) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 19 Operation of clock synchronous serial I/O function Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 22 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by setting the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 002616 Serial I/O1 control register Address 0FE016 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE SP detector Clock control circuit Serial I/O synchronous clock selection bit P42/EXTC/SCLK BRG count source selection bit System clock 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 0FE216 ST/SP/PA generator P40/EXDREQ/RxD OE Receive buffer register Character length selection bit STdetector 7 bits Receive shift register 8 bits UART control register Address 0FE116 1/16 P41/EXDACK/TxD Character length selection bit Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 002716 Transmit shift register Address 002616 Data bus Fig. 20 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 Generated TSC=1 SP at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=1 Serial input RXD ST D0 D1 SP ST D0 RBF=0 RBF=1 D1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : T he transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : T he receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 21 Operation of UART serial I/O function Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 23 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION [Serial I/O Control Register (SIOCON)] 0FE016 The serial I/O control register contains eight control bits for the serial I/O function. [UART Control Register (UARTCON)] 0FE116 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. [Serial I/O Status Register (SIOSTS)] 002716 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Transmit Buffer/Receive Buffer Register (TB/ RB)] 002616 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is "0". [Baud Rate Generator (BRG)] 0FE216 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. sNotes on serial I/O When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled). Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 24 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 Serial I/O status register (SIOSTS : address 002716) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (returns "1" when read) b7 b0 Serial I/O control register (SIOCON : address 0FE016) BRG count source selection bit (CSS) 0: System clock 1: System clock/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P43 pin operates as ordinary I/O pin 1: P43 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P40-P43 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P40-P43 can operate as serial I/O pins) b7 b0 UART control regi ster (UART CON : address 0FE116) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (ST PS) 0: 1 stop bit 1: 2 stop bits Not used (return "0" when read) (This is a write disabled bit.) Not used (return "1" when read) Fig. 22 Structure of serial I/O control registers Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 25 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION USB FUNCTION 38K0 Group is equipped with a USB function control circuit (USBFCC) that enables effective interfacing with the host-PC. This circuit is in compliance with USB2.0's Full-Speed Transfer Mode (12 Mbps, equivalent to USB1.1). This circuit also supports all four transfer-types specified in the standard USB specification. The USBFCC has four endpoints that can select its transfer type. Although Endpoint 0 is fixed to Control Transfer, the Endpoints 1 to 3 can be set to Interrupt Transfer, Bulk Transfer, or Isochronous Transfer. A dedicated circuit automatically performs stage management for Control Transfer and packet management for transactions, which are necessary for matching of data transmit/receive timing, error detection, and retry after error. This dedicated control circuit enables the user to develop a program or timing design very easily. Each endpoint can be programmed for data transfer conditions so that the endpoints are adaptive for all USB device class transfer systems. The data buffer of each endpoint can be assigned to any area in the multi-channel RAM. This feature offers highly efficient memory usage by avoiding re-buffering and enabling simple data modification. The transmit/receive data is directly transferred to the data buffer via the control circuit (direct RAM access type) without disturbing the CPU operation. This mechanism enables the CPU to transfer data smoothly with no drop in performance. In addition to this buffer function, a double-buffer setting will keep a re-buffering stall at a minimum and increase the overall data throughput (max. 64 bytes X 2 channels). As other special signals control, the endpoints have detection functions for the USB bus reset signal, resume signal, suspend signal, and SOF signal, and also have a remote wake-up signal transmit function. When completing data transfer or receiving a special signal, the endpoint generates the corresponding interrupt to the CPU (3 vectors/18 factors). With all this essential yet comprehensive built-in hardware, your system using the 38K0 group will be ready for any USB application that comes its way. 38K0 Group MCU Built-in Peripheral Functions Program ROM CPU Interrupt request External MCU External Bus Interface (EXB) Multi-channel RAM USB Data transmit/Receive path [Direct RAM Access Type] USB Bus (USB-Host) Fig. 23 USB function overview USB Data Transfer The USB specification promises 12 Mbps data transfer in the fullspeed mode, that is equivalent to 1.5 M bytes per second of data transactions. However, in USB data transfer, bit-stuffing may be executed depending on the bit patterns of the transfer data, possibly resulting in 1-byte data (normally 8 bits) handled as up to 10 bits. Because USB uses asynchronous transfers, the clock cycle of the USB internal reference clock may change to adjust to the clock phase. Therefore, the access timing of the USBFCC for the multichannel RAM will change owing to the frequency of internal clock : When the USBFCC is operating at =8 MHZ, access for a normal transfer is performed every 5 to 6 cycles and access for a bit-stuffing transfer is performed in up to 7 cycles. If the EXB function is enabled in the above conditions, this function generates a maximum wait of 1 clock cycle, so that the access is performed every 4 to 8 cycles. When operating at = 6MHZ, a normal access is performed every 4 cycles. If the clock-phase correction of the reference clock occurs, access is performed every 3 to 5 cycles. If bit stuffing occurs at this clock rate, the access cycle will be extended to up to 6 cycles. When the EXB function that generates a maximum 1-wait cycle is used in this condition, the access cycle will be 2 (min.) to 7 (max.) cycles. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 26 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION USB Function Control Circuit (USBFCC) Block Diagram The following diagram shows the USBFCC block diagram. The circuit comprises: (1) Serial Interface Engine (SIE) (2) Device Control Unit (DCU) (3) Internal Memory Interface (MIF) (4) CPU Interface (CIF) USB Function Control Circuit DCU control SIE control DCU DCU status SIE status USB Transceiver CPU CIF MIF control SIE D0+ D0- MIF Transmit/Receive data Multi-Channel RAM Fig. 24 USB Function Control Circuit (USBFCC) block diagram (1) Serial Interface Engine (SIE) The SIE performs the following USB lower-layer protocols (packets, transactions): *Sampling of receive data and clock, generation of transmit clock *Serial-to-parallel conversion of transmit/receive data *NRZI (Non Return Zero Invert) encode/decode *Bit stuffing/unstuffing *SYNC (Synchronization Pattern) detection, EOP (End of Packet) detection *USB address detection, endpoint detection *CRC (Cyclic Redundancy Check) generation and checking (2) Device Control Unit (DCU) The DCU manages the following USB upper-layer protocols (address/endpoint and control-transfer sequence): *Status control for each endpoint *Control-transfer sequence control *Memory interface status control (3) Memory Interface (MIF) The MIF controls the flow of data transfer between the SIE and the multi-channel RAM under the management of the DCU. (4) CPU Interface (CIF) The CIF performs the following functions: *Mode setting via registers, DCU control signal generation, DCU status signal reading *Interrupt signal generation *Internal bus interface control. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 27 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION USB Port External Circuit Configuration The operation mode of the USB port driver circuit can be configured by USB control register (address 001016). Figure 25 and Figure 26 show the USB port external circuit block diagram. VREFCON 0 1 Hiz 3.3V output Low-power mode VREFE DVCC 0 1 Hiz 3.3V output Normal mode VREFE USBVREF status VREFCON USB Reference Voltage Circuit USBVREF 2.2 F 0.1 F TRONCON TRON TRONE Full Speed 1.5 k D0+ 27 XOUT PLL fVCO "1" fUSB "0" UCLKCON USB Module USBE + USBDIFE USBE Full Speed D0- 27 USBE Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V VCC 5.25V) 3.0V to 3.6V (Note) USBVREF 0.1 F TRON TRONCON TRONE Full Speed 1.5 k D0+ 27 XOUT PLL fVCO "1" fUSB "0" UCLKCON USB Module USBE + USBDIFE USBE Full Speed D0- 27 USBE Note: In Vcc = 3.0 V to 3.6 V connect this pin to Vcc. Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V VCC 4.0V) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 28 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Endpoint Buffer Area Setting The buffer area used in data transfer can be assigned to any area of the multi-channel RAM for each endpoint. qBuffer area beginning address The buffer area configuration register (address 0FED16) defines the beginning address of the buffer area (every 32 bytes) for each Endpoint. However, the only RAM area is configurable. *00h [Address 000016], 01h [Address 002016]: Not configurable *02h [Address 004016] to 1Fh [Address 03E016]: Configurable qInterrupt-source dependant buffer area offset address An offset value is added to the beginning address of each source, which is specified by the interrupt source register (address 001D16), for each endpoint. This section describes in detail the beginning address specified by the buffer area set register as offset address 00h, according to each endpoint. (1) Endpoint 00 Endpoint 00 has two kinds of interrupt sources for accessing the buffer. The respective address offsets are: *BSRDY00 (SETUP Buffer Ready Interrupt): Offset address = 00h *BRDY00 (OUT or IN Buffer Ready Interrupt): Offset address = 08h (2) Endpoint 01 The buffer area offset address for each interrupt source for of Endpoint 01 varies according to the contents of the EP01 set register (address 001916). *In single buffer mode (DBLB01 = "0"): Endpoint 01 has only one interrupt source for accessing the buffer. B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h Memory 0FED16 00 0FED16 = 15h 000016 002016 SFR Disabled to be used 01 02 03 0000 0010 1010 0000 004016 006016 RAM 02A016 15 03E016 1F Fig. 27 Example setting of buffer area beginning address *In double buffer mode (DBLB01 = "1"): Endpoint 01 has two kinds of interrupt sources for accessing the buffer. B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h B1RDY01 (Buffer 1 Ready Interrupt): The offset address varies according to the double buffer beginning address set bit (BSIZ01). -Offset address = 08h when BSIZ01 = 00 -Offset address = 10h when BSIZ01 = 01 -Offset address = 40h when BSIZ01 = 10 -Offset address = 80h when BSIZ01 = 11 (3) Endpoints 02 and 03 Same as Endpoint 01. Notes The selected RAM area must be within addresses 004016 to 03FF16. Make sure the buffer area beginning address is set in agreement with the offset address and the number of transmit/receive data bytes. This is particularly important when in the double buffer mode or when handling 64-byte data. (a) When selecting Endpoint 00 (b) When selecting Single Buffer Mode (c) When selecting Double Buffer Mode (when BSIZ01 = 11) Memory 02A016 B0RDY01 Offset 00h Memory 02A016 BSRDY00 02A816 BRDY00 Offset 00h Memory 02A016 Offset 00h 08h B0RDY01 032016 B1RDY01 80h Fig. 28 Examples of interrupt source dependant buffer area offset address Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 29 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION USB Interrupt Function USB Interrupt Control Circuit (USBINTCON) has 3 requests and 16 USB-device interrupt request sources. Each interrupt source register enables the user to easily determine which interrupt has occurred. Table 7 shows the list of USB interrupt sources. Table 7 USB interrupt sources Interrupt request bit (IREQ1: Address 003C16) USB bus reset USB interrupt bit (USBIREQ: Address 001716) -- Interrupt source At USB bus reset signal detection: After enabling the USB module (USBE = "1"), an interrupt request occurs when 2.5 s SE0 state is detected in D0+/D0- port. (Equivalent to 120-clock length when fUSB = 48 MHz) At SOF packet receive: After enabling the USB module (USBE = "1"), an interrupt request occurs when SOF packet is detected in D0+/D0- port. Its occurrence does not depend on frame-time or CRC value after SOF packet is transferred. (Normally, SOF packet detection occurs only when fUSB = 48 MHz) At Endpoint 00 data transfer complete: *Buffer ready (read/write enabled state) *Control transfer completed *Status stage transition *SETUP buffer ready (read enabled state) *Control transfer error At Endpoint 01 data transfer complete: *Buffer 0 ready (read/write enabled state) *Buffer 1 ready (read/write enabled state) *Transfer error At Endpoint 02 data transfer complete: *Buffer 0 ready (read/write enabled state) *Buffer 1 ready (read/write enabled state) *Transfer error At Endpoint 03 data transfer complete: *Buffer 0 ready (read/write enabled state) *Buffer 1 ready (read/write enabled state) *Transfer error At suspend signal detection: After enabling the USB module (USBE = "1"), an interrupt request occurs when 3 ms J state is detected in D0+/D0- port. (Equivalent to 144,000 clock-length when fUSB = 48MHz) At resume signal detection: After enabling the USB module (USBE = "1") and resume interrupt (RSME = "1"), an interrupt request occurs when a bus state change (J state to SE0 or K state) is detected in D0- port. USB SOF -- USB device EP00 EP01 EP02 EP03 SUS RSM Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 30 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION [EPXXREG5] [USBIREQ] [USBICON] [EP00REQ] BRDY00 CTEND00 CTSTS00 BSYDY00 ERR00 [EP01REQ] B0RDY01 B1RDY01 ERR01 EP01 EP01E EP00 EP00E USB device interrupt request [EP02REQ] B0RDY02 B1RDY02 ERR02 [EP03REQ] B0RDY03 B1RDY03 ERR03 EP03 EP03E EP02 EP02E SUSE SUS RSME RSM Fig. 29 USB device interrupt control Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 31 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION USB Register List The USB register list is shown below. Address Register Name SYMBOL USB SFR bit 7 USBE bit 6 UCLKCON bit 5 USBDIFE bit 4 VREFE bit 3 VREFCON USBADD0[6:0] FNUM[7:0] RSME RSM SUSE SUS EP03E EP03 EP02E EP02 FNUM[10:8] EP01E EP00E EP01 EP00 EPIDX[1:0] bit 2 TRONE bit 1 TRONCON bit 0 WKUP AD0E 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 0FEC16 0FED16 (1) Endpoint 00 001916 001A16 001B16 001C16 001D16 001E16 001F16 0FEC16 0FED16 (2) Endpoint 01 001916 001A16 001B16 001C16 001D16 001E16 001F16 0FEC16 0FED16 (3) Endpoint 02 001916 001A16 001B16 001C16 001D16 001E16 001F16 0FEC16 0FED16 (4) Endpoint 03 001916 001A16 001B16 001C16 001D16 001E16 001F16 0FEC16 0FED16 USB control register USB function enable register USB function address register Frame number register Low Frame number register High USB interrupt source enable register USB interrupt source register Endpoint index register Endpoint field register 1 Endpoint field register 2 Endpoint field register 3 Endpoint field register 4 Endpoint field register 5 Endpoint field register 6 Endpoint field register 7 Endpoint field register 8 Endpoint field register 9 USBCON USBAE USBA0 FNUML FNUMH USBICON USBIREQ USBINDEX EPXXREG1 EPXXREG2 EPXXREG3 EPXXREG4 EPXXREG5 EPXXREG6 EPXXREG7 EPXXREG8 EPXXREG9 EP00 stage register EP00 control register 1 EP00 control register 2 EP00 control register 3 EP00 interrupt source register EP00 byte number register EP00STG EP00CON1 EP00CON2 EP00CON3 EP00REQ EP00BYT ERR00 BSRDY00 SETUP00 PID00[1:0] BVAL00 CTENDE00 CTSTS00 CTEND00 BRDY00 BBYT00[3:0] EP00 buffer area set register EP00BUF BADD00[4:0] EP01 set register EP01 control register 1 EP01 control register 2 EP01 control register 3 EP01 interrupt source register EP01 byte number register 0 EP01 byte number register 1 EP01 MAX. packet size register EP01 buffer area set register EP01CFG EP01CON1 EP01CON2 EP01CON3 EP01REQ EP01BYT0 EP01BYT1 EP01MAX EP01BUF TYP01[1:0] DIR01 ITMD01 SQCL01 DBLB01 ERR01 B0BYT01[6:0] B1BYT01[6:0] MXPS01[6:0] BADD01[4:0] BSIZ01[1:0] PID01[1:0] B0VAL01 B1VAL01 B1RDY01 B0RDY01 EP02 set register EP02 control register 1 EP02 control register 2 EP02 control register 3 EP02 interrupt source register EP02 byte number register 0 EP02 byte number register 1 EP02 MAX. packet size register EP02 buffer area set register EP02CFG EP02CON1 EP02CON2 EP02CON3 EP02REQ EP02BYT0 EP02BYT1 EP02MAX EP02BUF TYP02[1:0] DIR02 ITMD02 SQCL02 DBLB02 ERR02 B0BYT02[6:0] B1BYT02[6:0] MXPS02[6:0] BADD02[4:0] BSIZ02[1:0] PID02[1:0] B0VAL02 B1VAL02 B1RDY02 B0RDY02 EP03 set register EP03 control register 1 EP03 control register 2 EP03 control register 3 EP03 interrupt source register EP03 byte number register 0 EP03 byte number register 1 EP03 MAX. packet size register EP03 buffer area set register EP03CFG EP03CON1 EP03CON2 EP03CON3 EP03REQ EP03BYT0 EP03BYT1 EP03MAX EP03BUF TYP03[1:0] DIR03 ITMD03 SQCL03 DBLB03 ERR03 B0BYT03[6:0] B1BYT03[6:0] MXPS03[6:0] BADD03[4:0] BSIZ03[1:0] PID03[1:0] B0VAL03 B1VAL03 B1RDY03 B0RDY03 : Not used Fig. 30 USB related registers Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 32 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION USB Related Registers The USB related registers are shown below. b7 b0 USB control register (USBCON) [address 001016] Bit symbol WKUP TRONCON TRONE VREFCON VREFE USBDIFE UCLKCON USBE At reset RW H/W S/W 0 : Returning to BUS idle state by writing "1" first and 0 Remote wakeup bit - OO then "0". (Remote wakeup signal) 1 : K-state output 0 : "L" output mode (valid in TRONE = "1") TrON output control bit 0 - OO 1 : "H" output mode (valid in TRONE = "1") 0 : TrON port output disabled (Hi-Z state) TrON output enable bit 0 - OO 1 : TrON port output enabled USB reference voltage control bit 0 : Normal mode (valid in VREFE = "1") 0 - OO 1 : Low current mode (valid in VREFE = "1") USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled 0 - OO 1 : USB reference voltage circuit operation enabled USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled 0 - OO 1 : Upstream--port difference input circuit operation enabled 0 : External oscillating clock f(XIN) USB clock select bit 0 - OO 1 : PLL circuit output clock fVCO USB module operation enable bit 0 : USB module reset 0 - OO 1 : USB module operation enabled Bit name Function -: State remaining Fig. 31 Structure of USB control register b7 b0 0 00 000 0 USB function enable register (USBAE) [address 001116] Bit symbol AD0E b7:b1 Bit name USB function enable bit Not used Function 0: USB function address register invalidated 1: USB function address register validated Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO - - OO -: State remaining Fig. 32 Structure of USB function enable register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 33 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 USB function address register (USBA0) [address 001216] Bit symbol USBADD0 [6:0] b7 Bit name USB function address bit Function In AD0E = "0", this value changes after writing. In AD0E = "1", this value changes after completion of SET_ADDRESS control transferring. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 0 OO Not used - - OO -: State remaining Fig. 33 Structure of USB function address register b7 b0 Frame number register Low (FNUML) [address 001416] Bit symbol FNUM [7:0] Bit name Frame number low bit Function The frame number is updated at SOF reception. At reset RW H/W S/W InIn- O definite definite Fig. 34 Structure of Frame number register Low b7 b0 0 00 00 Frame number register High (FNUMH) [address 001516] Bit symbol FNUM [10:8] b7:b3 Bit name Frame number high bit Not used Function The frame number is updated at SOF reception. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W InIn- O definite definite - - OO -: State remaining Fig. 35 Structure of Frame number register High Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 34 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 USB interrupt source enable register (USBICON) [address 001616] Bit symbol EP00E EP01E EP02E EP03E b5:b4 SUSE RSME Bit name USB function/Endpoint 0 interrupt enable bit USB function/Endpoint 1 interrupt enable bit USB function/Endpoint 2 interrupt enable bit USB function/Endpoint 3 interrupt enable bit Not used Suspend interrupt enable bit Resume interrupt enable bit Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Write "0" when writing. "0" is read when reading. 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW H/W S/W 0 0 OO 0 0 0 - 0 0 0 0 0 - 0 0 OO OO OO OO OO OO -: State remaining Fig. 36 Structure of USB interrupt source enable register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 35 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 USB interrupt source register (USBIREQ) [address 001716] Bit symbol EP00 Bit name USB function/Endpoint 0 interrupt bit EP01 USB function/Endpoint 1 interrupt bit EP02 USB function/Endpoint 2 interrupt bit EP03 USB function/Endpoint 3 interrupt bit b5:b4 SUS Not used Suspend interrupt bit RSM Resume interrupt bit At reset RW H/W S/W This bit is set to "1" when any one of EP00 interrupt 0 0 O source register's bits at least is set to "1". This bit is cleared to "0" by clearing EP00 interrupt source register to "0016". Writing to this bit causes no state change. This bit is set to "1" when any one of EP01 interrupt 0 0 O source register's bits at least is set to "1". This bit is cleared to "0" by clearing EP01 interrupt source register to "0016". Writing to this bit causes no state change. This bit is set to "1" when any one of EP02 interrupt 0 0 O source register's bits at least is set to "1". This bit is cleared to "0" by clearing EP02 interrupt source register to "0016". Writing to this bit causes no state change. This bit is set to "1" when any one of EP03 interrupt 0 0 O source register's bits at least is set to "1". This bit is cleared to "0" by clearing EP03 interrupt source register to "0016". Writing to this bit causes no state change. Write "0" when writing. - - OO "0" is read when reading. 0 : No interrupt request issued 0 0 OO 1 : Interrupt request issued This bit is set to "1" when detecting 3 ms or more of Jstate, using USB clock (fUSB) at 48 MHz. "0" can be set by software, but "1" cannot be set. This bit is set to "1" when the USB bus state changes 0 0 O from J-state to K-state or SE0 in the resume interrupt enable bit = "1". It is also "1" in the condition of internal clock stopped. This bit is cleared to "0" by clearing the resume interrupt enable bit. Writing to this bit causes no state change. Function -: State remaining Fig.37 Structure of USB interrupt source register b7 b0 0 00 00 0 Endpoint index register (USBINDEX) [address 001816] Bit symbol Bit name Function b1 b0 0 0 : Endpoint 0 0 1 : Endpoint 1 1 0 : Endpoint 2 1 1 : Endpoint 3 Write "0" when writing. "0" is read when reading. EPIDX [1:0] Endpoint index bit At reset RW H/W S/W 0 - OO b7:b3 Not used - - OO -: State remaining Fig. 38 Structure of Endpoint index register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 36 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (1) Endpoint 00 b7 b0 0 0 0 00 00 EP00 stage register (EP00STG) [address 001916] Bit symbol SETUP00 Bit name SETUP packet detection bit Function This bit is set to "1" at reception of SETUP packet. Writing "0" to this bit clears this bit if the next SETUP token does not occur. Writing "1" to this bit causes no state change of the status flags. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 1 1 OO b7:b1 Not used - - OO -: State remaining Fig. 39 Structure of EP00 stage register b7 b0 0 0 0 00 0 EP00 control register 1 (EP00CON1) [address 001A16] Bit symbol PID00 [1:0] Bit name Response PID bit Function b1 b0 0 0 : NAK 0 1 : Automatic response (ACK, NAK, DATA0, DATA1) 1 X : STALL At occurrence of control transfer error: B1 is set to "1" by the hardware. At reception of SETUP token: B1 and b0 are cleared to "0" by the hardware. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b2 Not used - - OO -: State remaining Fig. 40 Structure of EP00 control register 1 b7 b0 0 0 00 00 0 EP00 control register 2 (EP00CON2) [address 001B16] Bit symbol BVAL00 Bit name Buffer enable bit Function 0 : NAK transmission (SIE is disabled to read a buffer.) 1 : Transmitting/receiving data set state (SIE is possible to read from/write to a buffer.) At reception of SETUP token: This bit is cleared to "0" by the hardware. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b1 Not used - - OO -: State remaining Fig. 41 Structure of EP00 control register 2 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 37 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 00 00 0 EP00 control register 3 (EP00CON3) [address 001C16] Bit symbol Bit name Function 0 : NAK transmission in the status stage 1 : Control transfer completion enabled (SIE transmits NULL/ACK.) (valid in PID00 = "012") At reception of SETUP token: This bit is cleared to "0" by the hardware. Write "0" when writing. "0" is read when reading. CTENDE00 Control transfer completion enable bit At reset RW H/W S/W 0 - OO b7:b1 Not used - - OO -: State remaining Fig. 42 Structure of EP00 control register 3 b7 b0 000 EP00 interrupt source register (EP00REQ) [address 001D16] Bit symbol BRDY00 Bit name USB function/Endpoint 0 buffer ready interrupt bit Function CTEND00 CTSTS00 BSRDY00 ERR00 b7:b5 0: No interrupt request issued 1: Interrupt request issued This bit is set to "1" when the buffer is ready state (enabled to be read/written) on USB function/Endpoint 0. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 0 control 0: No interrupt request issued transfer completion interrupt bit 1: Interrupt request issued This bit is set to "1" when control transfer is completed (NULL/ACK transmission in the status stage) on USB function/Endpoint 0. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 0 status 0: No interrupt request issued 1: Interrupt request issued stage transition interrupt bit This bit is set to "1" when transition to status stage occurs in CTENDE00 = "0" (control transfer completion disabled) on USB function/Endpoint 0. "0" can be set by software, but "1" cannot be set. At reset RW H/W S/W 0 0 OO 0 0 OO 0 0 OO 0 0 OO 0 0 OO - - OO -: State remaining Fig. 43 Structure of EP00 interrupt source register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 38 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 0 EP00 byte number register (EP00BYT) [address 001E16] Bit symbol BBYT00 [3:0] b7:b4 Bit name Function Transmit/receive byte number bit OUT : The received byte number is automatically set. IN : Set the transmitting byte number. Write 0 when writing. Not used 0 is read when reading. At reset RW H/W S/W 0 -- OO -- -- OO --: State remaining Fig. 44 Structure of EP00 byte number register b7 b0 0 00 EP00 buffer area set register (EP00BUF) [address 0FED16] Bit symbol BADD00 [4:0] Bit name EP00 beginning address set bit Function Set the beginning address of EP00's buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 004016 0 0 0 1 1 : 006016 .............. 1 1 1 1 0 : 03C016 1 1 1 1 1 : 03E016 Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b5 Not used - - OO -: State remaining Fig. 45 Structure of EP00 buffer area set register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 39 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (2) Endpoint 01 b7 b0 EP01 set register (EP01CFG) [address 001916] Bit symbol BSIZ01 [1:0] DBLB01 SQCL01 ITMD01 DIR01 TYP01 [1:0] At reset RW H/W S/W Double buffer beginning address set In double buffer mode set the beginning address of 0 - OO buffer 1 area, using a relative value for the beginning bit address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : Single buffer mode Buffer mode select bit 0 - OO 1 : Double buffer mode 0 : Toggle bit clear disabled Sequence toggle bit clear bit 0 - OO 1 : Writing "1" clears the toggle bit and DATA0 is used as the next data PID. "0" is always read when reading. Interrupt toggle mode select bit 0 : Normal mode 0 - OO 1 : Continuous toggle mode (valid at Interrupt IN transfer) 0 : OUT (Data is received from the host.) Transfer direction bit 0 - OO 1 : IN (Data is transmitted to the host.) b7b6 Transfer type bite 0 - OO 0 0 : Transfer disabled 0 1 : Bulk transfer 1 0 : Interrupt transfer 1 1 : Isochronous transfer Bit name Function -: State remaining Fig. 46 Structure of EP01 set register b7 b0 000 0 0 0 EP01 control register 1 (EP01CON1) [address 001A16] Bit symbol PID01 [1:0] Bit name Response PID bit Function b1 b0 0 0 : NAK 0 1 : Automatic response (ACK, NAK, DATA0, DATA1) 1 X : STALL At occurrence of over-max. packet size : B1 is set to "1" by the hardware. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b2 Not used - - OO -: State remaining Fig. 47 Structure of EP01 control register 1 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 40 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 00 0 0 0 EP01 control register 2 (EP01CON2) [address 001B16] Bit symbol B0VAL01 Bit name Buffer 0 enable bit b7:b1 Not used At reset RW H/W S/W - OO When the selected endpoint is IN, writing "1" to this bit 0 makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing "1" to this bit makes data reception possible (SIE is possible to write). - - OO Write "0" when writing. Function "0" is read when reading. -: State remaining Fig. 48 Structure of EP01 control register 2 b7 b0 0000 000 EP01 control register 3 (EP01CON3) [address 001C16] Bit symbol B1VAL01 Bit name Buffer 1 enable bit b7:b1 Not used At reset RW H/W S/W - OO When the selected endpoint is IN, writing "1" to this bit 0 makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing "1" to this bit makes data reception possible (SIE is possible to write). In double buffer mode this bit is valid. - - OO Write "0" when writing. "0" is read when reading. Function -: State remaining Fig. 49 Structure of EP01 control register 3 b7 b0 0 0 0 0 0 EP01 interrupt source register (EP01REQ) [address 001D16] Bit symbol B0RDY01 Bit name Function B1RDY01 ERR01 b7:b3 USB function/Endpoint 1 buffer 0 0: No interrupt request issued ready interrupt bit 1: Interrupt request issued This bit is set to "1" when the buffer 0 is ready state (enabled to be read/written) on USB function/Endpoint 1. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 1 buffer 1 0: No interrupt request issued ready interrupt bit 1: Interrupt request issued In single buffer mode this bit is invalid. This bit is set to "1" when the buffer 1 is ready state (enabled to be read/written) on USB function/Endpoint 1 in double buffer mode. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 1 error 0: No interrupt request issued interrupt bit 1: Interrupt request issued This bit is set to "1" when STALL response occurs on USB function/Endpoint 1. "0" can be set by software, but "1" cannot be set. Not used Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 0 OO 0 0 OO 0 0 OO - - OO Fig. 50 Structure of EP01 interrupt source register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 41 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 EP01 byte number register 0 (EP01BYT0) [address 001E16] Bit symbol B0BYT01 [6:0] Bit name IN : Transmit byte number bit Function Single buffer mode: Set the transmitting byte number. Double buffer mode : Set the transmitting byte number of buffer 0. Single buffer mode : The received byte number is automatically set. Double buffer mode : The received byte number of buffer 0 is automatically set. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO OUT : Receive byte number bit 0 - O b7 Not used - - OO -: State remaining Fig. 51 Structure of EP01 byte number register 0 b7 b0 0 EP01 byte number register 1 (EP01BYT1) [address 001F16] Bit symbol B1BYT01 [6:0] Bit name IN : Transmit byte number bit Function Single buffer mode: These bits are invalid. Double buffer mode : Set the transmitting byte number of buffer 1. Single buffer mode: These bits are invalid. Double buffer mode : The received byte number of buffer 1 is automatically set. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO OUT : Receive byte number bit 0 - O b7 Not used - - OO -: State remaining Fig. 52 Structure of EP01 byte number register 1 b7 b0 0 EP01 MAX. packet size register (EP01MAX) [address 0FEC16] Bit symbol MXPS01 [6:0] b7 Bit name Max. packet size bit Not used Function IN : These bits are invalid. OUT : Set the maximum packet size. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO - - OO -: State remaining Fig. 53 Structure of EP01 MAX. packet size register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 42 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 00 0 EP01 buffer area set register (EP01BUF) [address 0FED16] Bit symbol BADD01 [4:0] Bit name EP01 beginning address set bit Function Set the beginning address of EP01's buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 004016 0 0 0 1 1 : 006016 .............. 1 1 1 1 0 : 03C016 1 1 1 1 1 : 03E016 Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b5 Not used - - OO -: State remaining Fig. 54 Structure of EP01 buffer area set register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 43 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (3) Endpoint 02 b7 b0 EP02 set register (EP02CFG) [address 001916] Bit symbol BSIZ02 [1:0] DBLB02 SQCL02 ITMD02 DIR02 TYP02 [1:0] At reset RW H/W S/W Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0 - OO area, using a relative value for the beginning address of bit buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : Single buffer mode Buffer mode select bit 0 - OO 1 : Double buffer mode 0 : Toggle bit clear disabled Sequence toggle bit clear bit 0 - OO 1 : Writing "1" clears the toggle bit and DATA0 is used as the next data PID. "0" is always read when reading. Interrupt toggle mode select bit 0 : Normal mode 0 - OO 1 : Continuous toggle mode (valid at Interrupt IN transfer) 0 : OUT (Data is received from the host.) Transfer direction bit 0 - OO 1 : IN (Data is transmitted to the host.) b7b6 Transfer type bite 0 - OO 0 0 : Transfer disabled 0 1 : Bulk transfer 1 0 : Interrupt transfer 1 1 : Isochronous transfer Bit name Function -: State remaining Fig. 55 Structure of EP02 set register b7 b0 00 0 0 00 EP02 control register 1 (EP02CON1) [address 001A16] Bit symbol PID02 [1: 0] Bit name Response PID bit Function b1 b0 0 0 : NAK 0 1 : Automatic response (ACK, NAK, DATA0, DATA1) 1 X : STALL At occurrence of over-max. packet size : B1 is set to "1" by the hardware. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b2 Not used - - OO -: State remaining Fig. 56 Structure of EP02 control register 1 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 44 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 00 0 0 EP02 control register 2 (EP02CON2) [address 001B16] Bit symbol B0VAL02 Bit name Buffer 0 enable bit b7:b1 Not used At reset RW H/W S/W - OO When the selected endpoint is IN, writing "1" to this bit 0 makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing "1" to this bit makes data reception possible (SIE is possible to write). - - OO Write "0" when writing. Function "0" is read when reading. -: State remaining Fig. 57 Structure of EP02 control register 2 b7 b0 0 0 0 00 0 0 EP02 control register 3 (EP02CON3) [address 001C16] Bit symbol B1VAL02 Bit name Buffer 1 enable bit b7:b1 Not used At reset RW H/W S/W - OO When the selected endpoint is IN, writing "1" to this bit 0 makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing "1" to this bit makes data reception possible (SIE is possible to write). In double buffer mode this bit is valid. - - OO Write "0" when writing. Function "0" is read when reading. -: State remaining Fig. 58 Structure of EP02 control register 3 b7 b0 0 0 0 0 0 EP02 interrupt source register (EP02REQ) [address 001D16] Bit symbol B0RDY02 Bit name Function B1RDY02 ERR02 b7 to b3 USB function/Endpoint 2 buffer 0 0 : No interrupt request issued ready interrupt bit 1 : Interrupt request issued This bit is set to "1" when the buffer 0 is ready state (enabled to be read/written) on USB function/Endpoint 2. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 2 buffer 1 0 : No interrupt request issued ready interrupt bit 1 : Interrupt request issued In single buffer mode this bit is invalid. This bit is set to "1" when the buffer 1 is ready state (enabled to be read/written) on USB function/Endpoint 2 in double buffer mode. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 2 error 0 : No interrupt request issued interrupt bit 1 : Interrupt request issued This bit is set to "1" when STALL response occurs on USB function/Endpoint 2. "0" can be set by software, but "1" cannot be set. Not used Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 0 OO 0 0 OO 0 0 OO - - OO Fig. 59 Structure of EP02 interrupt source register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 45 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 EP02 byte number register 0 (EP02BYT0) [address 001E16] Bit symbol B0BYT02 [6:0] Bit name IN : Transmit byte number bit Function Single buffer mode: Set the transmitting byte number. Double buffer mode : Set the transmitting byte number of buffer 0. Single buffer mode: The received byte number is automatically set. Double buffer mode : The received byte number of buffer 0 is automatically set. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO OUT : Receive byte number bit 0 - O b7 Not used - - OO -: State remaining Fig. 60 Structure of EP02 byte number register 0 b7 b0 0 EP02 byte number register 1 (EP02BYT1) [address 001F16] Bit symbol B1BYT02 [6:0] Bit name IN : Transmit byte number bit Function Single buffer mode: These bits are invalid. Double buffer mode : Set the transmitting byte number of buffer 1. Single buffer mode: These bits are invalid. Double buffer mode : The received byte number of buffer 1 is automatically set. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO OUT : Receive byte number bit 0 - O b7 Not used - - OO -: State remaining Fig. 61 Structure of EP02 byte number register 1 b7 b0 0 EP02 MAX. packet size register (EP02MAX) [address 0FEC16] Bit symbol MXPS02 [6:0] b7 Bit name Max. packet size bit Not used Function IN : These bits are invalid. OUT : Set the maximum packet size. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO - - OO -: State remaining Fig. 62 Structure of EP02 MAX. packet size register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 46 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 00 0 EP02 buffer area set register (EP02BUF) [address 0FED16] Bit symbol BADD02 [4:0] Bit name EP02 beginning address set bit Function Set the beginning address of EP02's buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 004016 0 0 0 1 1 : 006016 .............. 1 1 1 1 0 : 03C016 1 1 1 1 1 : 03E016 Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b5 Not used - - OO -: State remaining Fig. 63 Structure of EP02 buffer area set register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 47 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (4) Endpoint 03 b7 b0 EP03 set register (EP03CFG) [address 001916] Bit symbol BSIZ03 [1:0] DBLB03 SQCL03 ITMD03 DIR03 TYP03 [1:0] At reset RW H/W S/W Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0 - OO area, using a relative value for the beginning address of bit buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : Single buffer mode Buffer mode select bit 0 - OO 1 : Double buffer mode 0 : Toggle bit clear disabled Sequence toggle bit clear bit 0 - OO 1 : Writing "1" clears the toggle bit and DATA0 is used as the next data PID. "0" is always read when reading. Interrupt toggle mode select bit 0 : Normal mode 0 - OO 1 : Continuous toggle mode (valid at Interrupt IN transfer) 0 : OUT (Data is received from the host.) Transfer direction bit 0 - OO 1 : IN (Data is transmitted to the host.) b7b6 Transfer type bit 0 - OO 0 0 : Transfer disabled 0 1 : Bulk transfer 1 0 : Interrupt transfer 1 1 : Isochronous transfer Bit name Function -: State remaining Fig. 64 Structure of EP03 set register b7 b0 000 0 0 0 EP03 control register 1 (EP03CON1) [address 001A16] Bit symbol PID03 [1:0] Bit name Response PID bit Function b1 b0 0 0 : NAK 0 1 : Automatic response (ACK, NAK, DATA0, DATA1) 1 X : STALL At occurrence of over-max. packet size : B1 is set to "1" by the hardware. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b2 Not used - - OO -: State remaining Fig. 65 Structure of EP03 control register 1 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 48 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 00 0 0 EP03 control register 2 (EP03CON2) [address 001B16] Bit symbol B0VAL03 Bit name Buffer 0 enable bit b7:b1 Not used At reset RW H/W S/W - OO When the selected endpoint is IN, writing "1" to this bit 0 makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing "1" to this bit makes data reception possible (SIE is possible to write). - - OO Write "0" when writing. Function "0" is read when reading. -: State remaining Fig. 66 Structure of EP03 control register 2 b7 b0 0000 000 EP03 control register 3 (EP03CON3) [address 001C16] Bit symbol B1VAL03 Bit name Buffer 1 enable bit b7:b1 Not used At reset RW H/W S/W - OO When the selected endpoint is IN, writing "1" to this bit 0 makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing "1" to this bit makes data reception possible (SIE is possible to write). In double buffer mode this bit is valid. - - OO Write "0" when writing. Function "0" is read when reading. -: State remaining Fig. 67 Structure of EP03 control register 3 b7 b0 0000 0 EP03 interrupt source register (EP03REQ) [address 001D16] Bit symbol B0RDY03 Bit name Function B1RDY03 ERR03 b7:b3 USB function/Endpoint 3 buffer 0 0 : No interrupt request issued ready interrupt bit 1 : Interrupt request issued This bit is set to "1" when the buffer 0 is ready state (enabled to be read/written) on USB function/Endpoint 3. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 3 buffer 1 0 : No interrupt request issued ready interrupt bit 1 : Interrupt request issued In single buffer mode this bit is invalid. This bit is set to "1" when the buffer 1 is ready state (enabled to be read/written) on USB function/Endpoint 3 in double buffer mode. "0" can be set by software, but "1" cannot be set. USB function/Endpoint 3 error 0 : No interrupt request issued interrupt bit 1 : Interrupt request issued This bit is set to "1" when STALL response occurs on USB function/Endpoint 3. "0" can be set by software, but "1" cannot be set. Not used Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 0 OO 0 0 OO 0 0 OO - - OO Fig. 68 Structure of EP03 interrupt source register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 49 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 EP03 byte number register 0 (EP03BYT0) [address 001E16] Bit symbol B0BYT03 [6:0] Bit name IN : Transmit byte number bit Function Single buffer mode: Set the transmitting byte number. Double buffer mode : Set the transmitting byte number of buffer 0. Single buffer mode: The received byte number is automatically set. Double buffer mode : The received byte number of buffer 0 is automatically set. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO OUT : Receive byte number bit 0 - O b7 Not used - - OO -: State remaining Fig. 69 Structure of EP03 byte number register 0 b7 b0 0 EP03 byte number register 1 (EP03BYT1) [address 001F16] Bit symbol B1BYT03 [6:0] Bit name IN : Transmit byte number bit Function Single buffer mode: These bits are invalid. Double buffer mode : Set the transmitting byte number of buffer 1. Single buffer mode: These bits are invalid. Double buffer mode : The received byte number of buffer 1 is automatically set. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO OUT : Receive byte number bit 0 - O b7 Not used - - OO -: State remaining Fig. 70 Structure of EP03 byte number register 1 b7 b0 0 EP03 MAX. packet size register (EP03MAX) [address 0FEC16] Bit symbol MXPS03 [6:0] b7 Bit name Max. packet size bit Not used Function IN : These bits are invalid. OUT : Set the maximum packet size. Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO - - OO -: State remaining Fig. 71 Structure of EP03 MAX. packet size register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 50 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 00 0 EP03 buffer area set register (EP03BUF) [address 0FED16] Bit symbol BADD03 [4:0] Bit name EP03 beginning address set bit Function Set the beginning address of EP03's buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 004016 0 0 0 1 1 : 006016 .............. 1 1 1 1 0 : 03C016 1 1 1 1 1 : 03E016 Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO b7:b5 Not used - - OO -: State remaining Fig. 72 Structure of EP03 buffer area set register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 51 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION EXTERNAL BUS INTERFACE (EXB) The external bus interface (EXB) controls the data transfer between the external MCU and the 38K0 group's CPU or its memory (multichannel RAM). The external bus interface is shown below. 38K0 group CPU CPU channel Program ROM Peripheral functions External MCU [Interrupt type] External bus interface (EXB) Memory channel [Direct RAM access type] Multichannel RAM USB USB bus (USB host) Fig. 73 External bus interface qCPU channel It is a data transfer course by the interrupt processing between the external MCU and the 38K0 group's CPU. qMemory channel It is a data transfer course by direct RAM access of the memory channel controller between the external MCU and the 38K0 group's memory (multichannel RAM) qData transfer of memory channel When the burst mode is selected with the burst bit of the memory channel operation mode register, data transfer can be carried out at the highest speed. After the external bus interface detects a rise of external read signal/write signal and synchronizes it with the internal clock , it completes the data transfer between the transmit/ receive buffer and the multichannel RAM in two clocks. However, the waiting time of two clocks at a maximum is generated to access the multichannel RAM in USB being operating because the USB has priority to access. Therefore, it is necessary to set up the access interval which fills the following timing with the external MCU bus side. In = 8 MHz, data transfer at about 2 Mbytes/second is possible at a maximum. When there is access simultaneously from the USB, it is about 1.3 Mbytes/second. In = 6 MHz, data transfer at about 1.5 Mbytes/second is possible at a maximum. When there is access simultaneously from the USB, it is about 1 Mbytes/second. Address CS, RD, WR, DMA acknowledge Access cycle time from externals: *3 clocks or more of + Signal delay time + Data setup time of external MCU in USB inactive *5 clocks or more of + Signal delay time + Data setup time of external MCU in USB active Fig. 74 Data transfer timing of memory channel Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 52 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION EXB Pin Assignment The external bus interface (EXB) pins are shown bellow. The 38K0 group can transmit/receive a data to/from an external MCU, using the following signals: *Control input signal ................ 4 (ExCS, ExA0, ExRD, ExWR) *Data input/output pin .............. 8 (DQ0 to DQ7) *Interrupt output signal ............ 1 (ExINT) Additionally, the DMA interface signal and the buffer status read select signal of 38K0 group can be set up per one by the program. *Control input signal ................ 3 (ExTC, ExDACK, ExRD, ExA1) *Interrupt output signal ............ 1 (ExDREQ) 38K0 group External bus interface (EXB) P34/ExCS [ L ] P37/ExA0 [address] P36/ExRD [ L ] P35/ExWR [ L ] P10/DQ0/AN0--P17/DQ7/AN7 [data] P33/ExINT [ L ] External pins External chip select External address External read External write External data External interrupt CPU 8 DMA request Terminal count DMA acknowledge Status read select P40/ExDREQ/RxD [ L ] P42/ExTC/SCLK [ L ] P41/ExDACK/TxD [ L ] P43/ExA1/SRDY [ H ] Multichannel RAM : Functions as normal ports just after reset. Fig. 75 External bus interface (EXB) pin assignment Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 53 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION EXB Block Diagram The block diagram of external bus interface (EXB) is shown below. The external bus interface (EXB) consists of: (1) External I/O interface part (2) CPU interface part (3) Internal memory interface part (4) Transmit/Receive data buffer part External I/O interface Configuration signal External I/O configuration register CPU interface Index register EXB interrupt source enable register Decoder data selector Cch_WR External MCU bus P34/ExCS Cch_RD TxB_RDY RxB_RDY CPU channel controller Command decoder P37/ExA0 P36/ExRD P35/ExWR Memory channel control Mch_RD Mch_WR Mch_TC mRX_enb mTX_enb Memory channel status Internal memory interface Memory channel operation mode register Memory address counter Memory address P41/ExDACK/TxD P42/ExTC/SCLK P43/ExA1/SRDY P33/ExINT Output selector End address register Mch_req FIFO_stt P40/ExDREQ/RxD Memory channel controller Request acknowledge MRDsel Memory channel transmit buffer control stt_sel ExOE Buf_WR Transmit/Receive data buffer Memory read data Transmit buffer register P10/DQ0/AN0- P17/DQ7/AN7 Memory write data Receive buffer register : Functions as normal ports just after reset. Fig. 76 Block diagram of external bus interface (EXB) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 54 of 112 Multichannel RAM HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (1) External I/O Interface Part The external I/O interface part consists of a command decoder and an output selector. A command decoder generates the following signals to each unit. qCPU interface part *CPU channel read (Cch_RD) *CPU channel write (Cch_WR) qInternal memory interface part *Memory channel read (Mch_RD) *Memory channel write (Mch_WR) *Memory channel terminal count (Mch_TC) qTransmit/receive data buffer part *Buffer write (Buf_WR) qExternal I/O interface part *Status selection (stt_sel) *Output enable (ExOE) Access to the CPU channel can be controlled only by setup of external signals. Access to the memory channel can be controlled by the value of the external I/O configuration register and the state (mRX_enb, mTX_enb signals) of the internal memory interface part. The output selector has the function which selects from the state of CPU channel (TxB_RDY and RxD_RDY) and the state of memory channel (Mch_req) as the signal assigned to P33/ ExINT pin and P40/ExDREQ/RxD pin. (2) CPU Interface Part The CPU interface part consists of the decoder/data selector of the CPU channel, the CPU write register and CPU channel controller qDecoder/data selector of CPU channel A write operation to the CPU register is performed by generating a write signal for each register with an address decode signal and a write signal. A read operation from the CPU register is performed by generating an output enable signal of the internal data bus with an module select signal and a read signal and generating a select signal for each register with an address decode signal. qCPU write register There are three CPU write registers as follows: *EXB interrupt source enable register *Index register *External I/O configuration register The EXB interrupt source register is a read-only register. A status signal of the CPU channel controller and a status signal of the memory channel controller in the internal memory interface part are generated. qCPU channel controller The CPU channel controller generates the following signals, using bits 0 and 1 (RXB_ENB, TXB_ENB) of EXB interrupt source enable register. *Memory channel transmitting buffer control signal (MRD_sel), generated in the internal memory interface part *CPU channel command signal (Cch_RD, Cch_WR), generated in the external I/O interface part *Signals RxB_RDY/RxB_full and TxB_RDY/TxB_empty, generated with read/write signals from the CPU channel Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 55 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (3) Internal Memory Interface Part The internal memory interface part consists of the CPU register and the memory channel controller. qCPU register The CPU register consists of the follows: *Memory channel operation mode register *Memory address counter *End address register The CPU can set the beginning address into the memory address counter when the memory channel operation enable bit (MC_ENB) of EXB interrupt source enable register is "0". When this bit is "1", the write operation from the CPU is invalid and each access from the external bus causes count-up operation. qMemory channel controller The CPU register consists of the follows: *Main sequencer *Internal memory request signal generating circuit *External memory channel request signal generating circuit *Address end detection circuit *Terminal end input processing circuit (5) External Pin The external bus interface has the following pins to connect with an external MCU bus. *Chip select ........................... P34/ExCS *Address ................................ P37/ExA0 *Data ...................................... P10/DQ0/AN0 to P17/DQ7/AN7 *Read .................................... P36/ExRD *Write ..................................... P35/ExWR *Interrupt request .................. P33/ExINT It also has the following pins to connect with an external DMAC. Each pin can be programmed for an ordinary port function or a DMA interface pin function. *DMA request ........................ P40/ExDREQ/RxD *DMA acknowledgment ......... P41/ExDACK/TxD *Terminal count ..................... P42/ExTC/SCLK It also has the status read select pin (P43/ExA1/SRDY pin) to confirm a ready status of the data buffer from an external MCU bus This pin functions as a port just after reset. The status read select function can be set by a program. *Status read select ................ P43/ExA1/SRDY qCPU channel: Communication with 38K0 group CPU When a read/write operation is performed from an external MCU bus in address signal ExA0 = "H", the interrupt is generated and the 38K0 group CPU can confirm its access. The 38K0 group CPU judges the interrupt source and it starts a data transmission/reception with an external MCU bus. qMemory channel: Communication with 38K0 group memory multichannel RAM When a read/write operation is performed from an external MCU bus in address signal ExA0 = "L", access to the multichannel RAM is performed. Then an address of the multichannel RAM is made by the external bus interface and it is increased at each access completion. Consequently, FIFO access is performed. Even if a read/write operation is performed in DACK = "L" instead of ExCS = "L" and ExA0 = "L", FIFO access to the multichannel RAM is performed. The beginning address and the end address must be set by the CPU in advance. (4) Transmit/Receive Data Buffer Part The transmit/receive data buffer part consists of the 8-bit transmit buffer register (TXBUF) and the 8-bit receive buffer register (RXBUF). Both CPU channel and memory channel use the same transmit buffer register/receive buffer register to transfer a data to an external MCU bus. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 56 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qP33/ExINT pin Any one of the following signals for this pin can be selected: *TxB_RDY (transmit buffer ready) output *RxB_RDY (receive buffer ready) output *Mch_req (memory channel request) output Either TxB_RDY or RxB_RDY is normally selected. The memory channel request is for an access request signal to the memory channel. In a small system, a data transfer processing to the internal memory is performed in the interrupt routine. According to that situation, the 38K0 group has the function automatically to switch an interrupt factor attached on the interrupt pin by program. qP40/ExDREQ/RxD pin This pin is a port at the initial state. Which signal can be set by program. *RxB_RDY (receive buffer ready) output *Mch_req (memory channel request) output Mch_req of DMAC is normally selected. The output method of the memory channel request signal depends on the burst bit (BURST) of memory channel operation mode register. When the burst bit is "0", this signal is periodically output at each 1-byte transfer. (See Figures 94 and 97.) When the burst bit is "1", this signal is continuously output while the memory address counter is counting from the beginning address to the end address (See Figures 95 and 98.) qP41/ExDACK/TxD pin This pin is a port at the initial state. The DMA acknowledge signal can be set by program. The DMA acknowledge signal DACK = "L" is the same state as that of CS = "L" and A0 = "L". Access to multichannel RAM is started by a rise of read signal or write signal which is set during this term. Note: If the DMA acknowledge signal and the chip select signal are simultaneously active (DACK = "L" and CS = "L"), also set the address signal A0 to "L". If A0 is "H", the memory channel and the CPU channel are activated simultaneously and it might cause some error. qP42/ExTC/SCLK pin This pin is a port at the initial state. The terminal count signal can be set by program. If the terminal count signal is set at one bus cycle while a memory channel operation write is being performed, the 38K0 group confirms that its bus cycle is the write cycle of the last data and sets the memory channel status bits to "112", and the interrupt is generated and the memory channel operation ends even if the memory address counter has not reached the end address. The CPU can obtain the last address where the data is written by reading out the value of memory address counter. (See Figure 96.) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 57 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION EXB Register List The EXB register list is shown below. Address Register Name SYMBOL EXB SFR bit7 bit6 bit5 bit4 bit3 bit2 MC_ENB MC_STS[1:0] 0 0 0 0 LOW_WIN[7:0] HIGH_WIN[7:0] 0 bit1 TXB_ENB TXB_EMPTY INDEX[2:0] bit0 RXB_EMB RXB_FULL 003016 003116 003316 003416 003516 EXB interrupt source enable register EXB interrupt source register EXB index register Register window 1 (low) Register window 2 (high) EXBICON EXBIREQ EXBINDEX EXBREG1 EXBREG2 : Not used 0 : "0" fixed Fig. 77 EXB related registers (1) *EXB interrupt source enable register This register enables/disables access from an external bus and an internal interrupt. *EXB interrupt source register This register indicates the state of CPU channel's transmit/receive buffer register and the memory channel. The same value can be read out from the external MCU bus by using the buffer status read select signal (A1 pin = "H"). *EXB index register/Register windows 1, 2 The accessible register is switched by treating addresses 003416 and 003516 as a register window depending on the value of EXB index register at address 003316. Index 0016 low high low high Register Name External I/O configuration register SYMBOL EXBCFGL EXBCFGH EXB SFR bit7 bit6 bit5 bit4 A1_CTR TC_CTR bit3 bit2 INT_CTR[2:0] DAK_CTR[1:0] bit1 bit0 EXB_CTR DRQ_CTR[1:0] 0116 low high Transmit/Receive buffer register RXBUF/TXBUF -- At CPU read : RXBUF[7:0] At CPU write : TXBUF[7:0] 0216 low high Memory channel ope- MCHMOD ration mode register -- Memory address counter MEMADL MEMADH End address register ENDADL ENDADH 0 0 0 0 0 0 0 0 END_A[7:0] 0 IM_A[7:0] 0 BURST MC_DIR[1:0] 0316 low high IM_A[10:8] 0416 low high END_A[10:8] : Not used 0 : "0" fixed Fig. 78 EXB related registers (2) *External I/O configuration register This register selects the function of each pin. *Transmit/Receive buffer register This register consists of the receive buffer register (RXBUF) and the transmit buffer register (TXBUF) *Memory channel operation mode register This register sets the operation mode of the memory channel. *Memory address counter This is a counter to set the beginning address which FIFO accesses. This register is increased by access from the external MCU bus. *End address register This register is to set the end address which FIFO accesses. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 58 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION EXB Related Registers The EXB related registers are shown below. b7 b0 00 0 0 0 EXB interrupt source enable register (EXBICON) [address 003016] (Note) Bit symbol RXB_ENB TXB_ENB MC_ENB Bit name Function At reset RW H/W S/W 0 - OO 0 0 - - OO OO b7:b3 CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled) 1 : Operation enabled (Receive buffer full interrupt enabled) CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled) 1 : Operation enabled (Transmit buffer empty interrupt enabled) 0 : Operation disabled (Memory channel operation end Memory channel operation interrupt disabled) enable bit 1 : Operation enabled (Memory channel operation end interrupt disabled) Write "0" when writing. Not used "0" is read when reading. - - OO -: State remaining Note: Do not set each bit simultaneously. Fig. 79 Structure of EXB interrupt source enable register b7 b0 0 0 0 0 EXB interrupt source register (EXBIREQ) [address 003116] (Note 1) Bit symbol RXB_FULL Bit name Receive buffer full bit Function 0 : Receive buffer empty 1 : Receive buffer full 0 : Transmit buffer full 1 : Transmit buffer empty b3b2 0 0 : Memory channel operation stopped 0 1 : Memory channel being operating; No external access 1 0 : Memory channel being operating; External accessing 1 1 : Memory channel operation end; Memory channel operation end interrupt generated Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 0 O- (Note 3) TXB_EMPTY Transmit buffer empty bit MC_STS [1:0] (Note 2) Memory channel status bits 0 0 0 (Note 4) O- O- 0 b7:b4 Not used - - OO -: State remaining Notes 1: When the the ExA1 pin control bit of external I/O configuration register is "1", the external MCU bus can read this register contents by setting the ExA1 pin to "H". 2: The memory channel status bits indicate the status of memory channel. In MC_ENB = "0" these bits are always "002". When the memory channel operation ends, these bits are set to "112" and the memory channel operation end interrupt is generated. These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing or not. 3: This bit is cleared to "0" when reading the transmit/receive buffer register in the CPU channel receive enable bit = "1" or when the CPU channel receive enable bit is "0". 4: This bit is cleared to "0" when writing to the transmit/receive buffer register in the CPU channel transmit enable bit = "1" or when the CPU channel transmit enable bit is "0". Fig. 80 Structure of EXB interrupt source register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 59 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 00 EXB index register (EXBINDEX) [address 003316] Bit symbol INDEX [2:0] Index bits Bit name b7:b3 Not used At reset RW H/W S/W - OO The accessible register, using the register window, 0 depends on these index bits contents as follows: b2b1b0 0 0 0 : External I/O configuration register 0 0 1 : Transmit/Receive buffer register 0 1 0 : Memory channel operation mode register 0 1 1 : Memory address counter 1 0 0 : End address register 1 0 1 : Do not set. 1 1 0 : Do not set. 1 1 1 : Do not set. - - OO Write "0" when writing. "0" is read when reading. Function -: State remaining Fig. 81 Structure of EXB index register b7 b0 Register window 1 (EXBREG1) [address 003416] Bit symbol LOW_WIN [7:0] - Bit name At reset RW H/W S/W In- O O The accessible register, using this register window, Independs on the EXB index register contents as definite definite follows: Index value "0016" : External I/O configuration register "0116" : Transmit/Receive buffer register "0216" : Memory channel operation mode register "0316" : Memory address counter "0416" : End address register Function Fig. 82 Structure of Register window 1 b7 b0 Register window 2 (EXBREG2) [address 003516] Bit symbol HIGH_WIN [7:0] - Bit name At reset RW H/W S/W In- O O The accessible register, using this register window, Independs on the EXB index register contents as definite definite follows: Index value : External I/O configuration register "0016" "0116" : Transmit/Receive buffer register : Memory channel operation mode register "0216" : Memory address counter "0316" : End address register "0416" Function Fig. 83 Structure of Register window 2 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 60 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416] Bit symbol EXB_CTR INT_CTR [2:0] Bit name EXB pin control bit (Pins P10 to P17, P30 to P34) P33/ExINT pin control bit Function 0 : Port 1 : EXB function pin Selects a signal of P33/ExINT pin. ON/OFF is programmed by each bit. An output logical sum of P33/ExINT pins set for ON are performed and it is output as an "L" active signal. b3b2b1 0 0 1 : RxB_RDY (RxBuf ready) output 0 1 0 : TxB_RDY (TxBuf ready) output 1 0 0 : Mch_req (Memory channel request) output Others : Do not set. 0 : Port 1 : A1 input (used to read status) Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO 0 - OO A1_CTR b7:b5 P43/ExA1 pin control bit Not used 0 - - - OO OO -: State remaining Fig. 84 Index00[low]; Structure of External I/O configuration register b7 b0 0 0 0 Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516] Bit symbol DRQ_CTR [1:0] Bit name P40/ExDREQ/RxD pin control bit Function b1b0 0 0 : Port 0 1 : Do not set. 1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output 1 1 : ExDREQ function; Mch_req (Memory channel request) output Specifies P41/ExDACK/TxD pin function. Selects which mode; requiring read or write signal, or not requiring it for use of DMA acknowledge function. b3b2 0 0 : Port 0 1 : Do not set. 1 0 : ExDACK function; DMA acknowledge input (Mode for read and write signals used together) 1 1 :ExDACK function; DMA acknowledge input (Mode for read and write signals not required) 0 : Port 1 : ExTC (terminal count) input Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO DAK_CTR [1:0] P41/ExDACK/TxD pin control bit 0 - OO TC_CTR b7:b5 P42/ExTC/SCLK pin control bit Not used 0 - - - OO OO -: State remaining Fig. 85 Index00[high]; Structure of External I/O configuration register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 61 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416] Bit symbol RXBUF/ TXBUF - Bit name At reset RW H/W S/W - OO The data received from an external bus is written here 0 at the rise timing of external write signal. The data transmitted to an external bus is written here at the timing of internal CPU write or memory write. Function The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the CPU has written to this address is stored in the transmit buffer register (TXBUF). However, do not perform write operation with the CPU to this address if the memory channel direction control bits of memory channel operation mode register is "102" (transmit mode) and the memory channel status bits of EXB interrupt source register are "012" or "102" (memory channel being operating). Fig. 86 Index01[low]; Structure of Transmit/Receive buffer register b7 b0 0 0 0 0 0 Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416] Bit symbol MC_DIR [1:0] Bit name Memory channel direction control bit Function b1b0 0 0 : Operation disabled 0 1 : Receive mode 1 0 : Transmit mode 1 1 : Do not set. 0 : Cycle mode (each byte transfer according to assertion or negation) 1 : Burst mode (continuous transfer till the terminal count) Write "0" when writing. "0" is read when reading. At reset RW H/W S/W 0 - OO BURST Burst bit 0 - OO b7:b3 Not used - - OO -: State remaining Fig. 87 Index02[low]; Structure of Memory channel operation mode register b7 b0 Index = 0316 : Memory address counter (MEMADL) [address 003416] Bit symbol IM_A [7:0] - Bit name At reset RW H/W S/W OO Register to set the low-order address of memory 0 - channel operation beginning. This contents are increased each time one memory access ends. Function Fig. 88 Index03[low]; Structure of Memory address counter Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 62 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 0 0 Index = 0316 : Memory address counter (MEMADH) [address 003516] Bit symbol IM_A [10:8] - Bit name b7:b3 Not used At reset RW H/W S/W Register to set the high-order address of memory 0 - OO channel operation start. This contents are increased each time one memory access ends. Write "0" when writing. - - OO "0" is read when reading. Function -: State remaining Fig. 89 Index03[high]; Structure of Memory address counter b7 b0 Index = 0416 : End address register (ENDADL) [address 003416] Bit symbol END_A [7:0] - Bit name At reset RW H/W S/W Register to set the low-order address of memory 0 - OO channel operation end. Function -: State remaining Fig. 90 Index04[low]; Structure of End address register b7 b0 0 0 0 0 0 Index = 0416 : End address register (ENDADH) [address 003516] Bit symbol END_A [10:8] b7:b3 - Not used Bit name At reset RW H/W S/W Register to set the high-order address of memory 0 - OO channel operation end. Write "0" when writing. - - OO "0" is read when reading. Function -: State remaining Fig. 91 Index04[high]; Structure of End address register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 63 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION EXB Operation Timing Diagram (1) CPU Channel Receiving Operation CPU channel receiving operation is shown bellow. Address ExA0 Chip select ExCS Read ExRD A0 = "1" CS = "0" A0 = "1" CS = "0" Write ExWR Data DQ0 to DQ7 #0 #1 Internal clock Interrupt request ExINT [RxB_RDY] Receive buffer full bit RXB_FULL Receive buffer RXBUF Transmit buffer TXBUF CPU channel receive enable bit RXB_ENB Receive buffer read #0 #1 RxB_RDY RxB_RDY INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt) RXB_ENB (CPU channel receive enable) = "1" (Receive buffer full interrupt enabled) Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to "L". If the CPU channel receive enable bit (RXB_ENB) is "0", both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an external are inactive. When a write operation is performed from an external MCU bus in the condition of ExCS = "L" and WxA0 = "H", it will result in as follows: * The data is written into the receive buffer (RXBUF) * Negation of the receive buffer ready signal (RxB_RDY) to an external is made * The RXB_FULL interrupt is generated. When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to "0". Fig. 92 CPU channel receiving operation Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 64 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (2) CPU Channel Transmitting Operation CPU channel transmitting operation is shown bellow. Address ExA0 Chip select ExCS Read ExRD Write ExWR Data DQ0 to DQ7 A0 = "1" CS = "0" ' A0 = "1" CS = "0" #0 #1 Internal clock Interrupt request ExINT [TxB_RDY] Transmit buffer empty bit TXB_EMPTY Receive buffer RXBUF Transmit buffer TXBUF CPU channel transmit enable bit TXB_ENB Transmit data write #0 #1 TxB_RDY TxB_RDY ' INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt) TXB_ENB (CPU channel transmit enable) = "1" (Transmit buffer empty interrupt enabled) Writing the command for enabling operation generates TXB_EMPTY interrupt. If the CPU channel transmit enable bit (TXB_ENB) is "0", both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to an external are inactive. When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared to "0" and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made. When a read operation is performed from an external MCU bus in the condition of ExCS = "L" and ExA0 = "H", it will result in as follows: * The contents of the transmit buffer (TXBUF) is read out * The transmit buffer empty bit (TXB_EMPTY) is set to "1" * Negation of the transmit buffer ready signal (TxB_RDY) to an external is made. Fig. 93 CPU channel tranmitting operation Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 65 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (3) Memory Channel Receiving Operation (1)Cycle Mode Memory channel receiving operation (1) is shown bellow. Address ExA0 Chip select ExCS DMA acknowledge ExDACK Read ExRD Write ExWR Data DQ0 to DQ7 Internal clock DMA request ExDREQ Mch_req A0 = "0" CS = "0" ' A0 = "0" CS = "0" ' #0 #1 Mch_req mWR mWR detection detection #0 #1 Receive buffer RXBUF Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access req req 0 1 2 3 5 Memory address Counter end 010016 010116 010216 Acknowledgment of internal memory access ack ack MC_ENB (Memory channel operation enable) = "1" (Operation start) In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the memory channel request which synchronized with a rise of is made. When the external MCU bus is in the condition of ExCS = "L" and ExA0 = "L" or a fall of ExWR is detected in the condition of ExDACK = "L", negation of the memory channel request which synchronized with a rise of is made. When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of is activated and a data is written in the internal memory within two clocks at a minimum. The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made. When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel request is not made and the memory channel operation end interrupt is generated. Fig. 94 Memory channel receiving operation (1) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 66 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (4) Memory Channel Receiving Operation (2)Burst Mode Memory channel receiving operation (2) is shown bellow. Address ExA0 Chip select ExCS DMA acknowledge ExDACK Read ExRD A0 = "x" CS = "1" Dack = "0" A0 = "x" CS = "1" Dack = "0" ' A0 = "x" CS = "1" Dack = "0" Write ExWR Data DQ0 to DQ7 Internal clock DMA request ExDREQ Mch_req #0 #1 ' #2 mWR mWR detection detection #0 #1 #2 Receive buffer RXBUF Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access req req req 0 1 2 3 5 Memory address Counter end Burst end 010016 010116 010216 010316 Acknowledgment of internal memory access ack ack ack MC_ENB (Memory channel operation enable) = "1" (Operation start) In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized with a rise of is made. When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of is activated and a data is written in the internal memory within two clocks at a minimum. The memory address counter is increased simultaneously at the former data write completion. When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the memory channel request which synchronized with the following is made. the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end interrupt is generated. When Fig. 95 Memory channel receiving operation (2) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 67 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (5) Memory Channel Receiving Operation (3)Burst Mode (Terminal Count) Memory channel receiving operation (3) is shown bellow. ' Address ExA0 Chip select ExCS DMA acknowledge ExDACK Terminal count ExTC Write ExWR Data DQ0 to DQ7 Internal clock DMA request ExDREQ Mch_req #0 #1 ' A0 = "x" CS = "1" Dack = "0" A0 = "x" CS = "1" Dack = "0" ' TC mWR mWR detection detection #0 #1 Receive buffer RxBuf mTC detection TC synchronizing TC end Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access req 0 1 2 3 (5) 5 ' ' ' ' Memory address Counter end Burst end 010016 010116 010216 Acknowledgment of internal memory access ack ack MC_ENB (Memory channel operation enable) = "1" (Operation start) When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of is made. When the write operation to the end address has been completed, the memory channel operation end interrupt is generated. Fig. 96 Memory channel receiving operation (3) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 68 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (6) Memory Channel Transmitting Operation (1)-Cycle Mode Memory channel transmitting operation (1) is shown bellow. Address ExA0 Chip select ExCS DMA acknowledge ExDACK Read ExRD Write ExWR Data DQ0 to DQ7 Internal clock DMA request ExDREQ Mch_req Mch_req #0 #1 A0 = "x" CS = "1" Dack = "0" ' A0 = "x" CS = "1" Dack = "0" ' mRD mRD detection detection Transmission completed Transmit buffer TXBUF #0 #1 Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access req 0 1 2 3 4 5 req Memory address Counter end 010016 010116 010216 Acknowledgment of internal memory access ack ack MC_ENB (Memory channel operation enable) = "1" (Operation start) In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal memory access sequence which synchronized with a rise of is activated. A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address counter is simultaneously increased and assertion of the memory channel request is made. When the external MCU bus is in the condition of ExCS = "L" and ExA0 = "L" or a fall of ExRD is detected in the condition of ExDACK = "L", negation of the memory channel request which synchronized with a rise of is made. When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of is activated. A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address counter is simultaneously increased and assertion of the memory channel request is made. When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs. When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated. Fig. 97 Memory channel tranmitting operation (1) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 69 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (7) Memory Channel Transmitting Operation (2)-Burst Mode Memory channel transmitting operation (2) is shown bellow. Address ExA0 Chip select ExCS DMA acknowledge ExDACK Read ExRD Write ExWR Data DQ0 to DQ7 Internal clock DMA request ExDREQ A0 = "x" CS = "1" Dack = "0" A0 = "x" CS = "1" Dack = "0" ' A0 = "x" CS = "1" Dack = "0" ' #0 #1 #2 Mch_req mRD mRD detection detection Transmission completed Transmit buffer TXBUF Operation enabled #0 #1 #2 Main sequencer Memory channel operation end interrupt Internal memory access req req req 0 1 2 3 4 5 Memory address Counter end Burst end 010016 010116 010216 010316 Acknowledgment of internal memory access ack ack ack MC_ENB (Memory channel operation enable) = "1" (Operation start) In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with a rise of is activated. A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address counter is simultaneously increased and assertion of the memory channel request is made. When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of is activated. A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address counter is simultaneously increased. When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation of the memory channel request which synchronized with the following is made. When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated. Fig. 98 Memory channel tranmitting operation (2) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 70 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION MULTICHANNEL RAM The 38K0 group has the built-in multichannel RAM including the small logic circuit (RAM I/F) instead of ordinary RAM. The multichannel RAM has the USB channel and the EXB channel in addition to the CPU channel. The multichannel RAM controls access from CPU, USB and EXB, synchronizing control with . The USB transfer rate is about 1.5 Mbytes/second. Access to the multichannel RAM is performed at every about 5.3 clocks in = 8 MHz, or at every about 4 clocks in = 6 MHz. The USB's access has priority to the EXB's. The one wait function (ONW function) of 38000 series CPU is used internally to control access with the CPU. When receiving an access request from the USB or the EXB, the multichannel RAM outputs ONW signal to wait the CPU for one clock, and access of the USB or the EXB is performed. If the multichannel RAM is outputting ONW signal while the CPU is in the state of reading/writing for the RAM area, the CPU read cycle or write cycle is extended by 1 period of . No wait ONW = "H" No wait Except RAM No wait No RD/WR CPU bus cycle CPU AD RD/WR RAM area Except RAM RAM area USB REQ Multichannel RAM EXB REQ ONW RAM access right RAM bus cycle RAM RD/WR CPU USB CPU Fig. 99 Multichannel RAM timing diagram (no wait) One wait CPU accessing RAM at the latter part One wait Prohibiting continuous access of USB/EXB Prior CPU One wait USB having priority of USB/EXB simultaneous access Prior USB Prior CPU One wait 2-cycle wait (max.) for EXB Prior CPU CPU bus cycle CPU AD RD/WR RAM area RAM area RAM area RAM area USB REQ Multichannel RAM EXB REQ ONW RAM access right RAM bus cycle RAM RD/WR EXB CPU USB CPU USB CPU EXB CPU Fig. 100 Multichannel RAM timing diagram (one wait) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 71 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Multichannel RAM Operation Example The multichannel RAM operation example is shown below. This example shows the case that an external MCU uses the 38K0 group as a peripheral LSI (USB controller). The following explains that the external MCU reads out the data which is received via the USB. The data which is received via the USB is written into the multichannel RAM. Receive completion is propagated to the CPU. The external bus interface is activated owing to the CPU. (1) The external bus interface sets the data which is read from the multichannel RAM into the internal data buffer. (2) The external MCU reads out the data bus buffer of the external bus interface. (3) The above operation is repeated by the number of the received bytes. After that, the data transfer is completed. CPU Program ROM Peripheral functions External MCU Activating External MCU bus Notice of receive completion USB bus (USB host) External bus interface Multichannel RAM USB FIFO read of received data by External bus interface FIFO write of received data by USB Fig. 101 Multichannel RAM operation example Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 72 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION A/D CONVERTER The functional blocks of the A/D converter are described below. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(system clock) to 500 kHz or more during an A/D conversion. [AD Conversion Register 1, 2 (AD1, AD2)] 003716, 003816 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. Bit 7 of the AD conversion register 2 must be set to "0".Not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the AD conversion registers 1, 2 after A/D conversion is completed (in Figure 103). The 8-bit reading inclined to MSB is performed when reading the AD converter register 1 after A/D conversion is started or reset; and when the AD converter register 1 is read after reading the AD converter register 2, the 8-bit reading inclined to LSB is performed. b7 b0 AD control register (ADCON : address 003616) Analog input pin selection bits 0 0 0 : P10/DQ0/AN0 0 0 1 : P11/DQ1/AN1 0 1 0 : P12/DQ2/AN2 0 1 1 : P13/DQ3/AN3 1 0 0 : P14/DQ4/AN4 1 0 1 : P15/DQ5/AN5 1 1 0 : P16/DQ6/AN6 1 1 1 : P17/DQ7/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (indefinite at read) (These bits are write disabled bits.) [AD Control Register (ADCON)] 003616 The AD control register controls the A/D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at "0" during an A/D conversion, and changes to "1" when an A/D conversion ends. Writing "0" to this bit starts the A/D conversion. Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSS into 1024, and that outputs the comparison voltage. The A/D converter successively compares the comparison voltage Vref in each mode, dividing the VREF voltage (see below), with the input voltage. * 10-bit reading VREF Vref = 1024 n (n = 0-1023) * 8-bit reading Vref = VREF n (n = 0-255) 256 Note : Bits 2 to 7 of address 003816 become "0" at reading. Fig. 102 Structure of AD control register 10-bit reading (Read address 003816 before 003716) b7 (address 003816) 0 b7 (address 003716) b0 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b0 Channel Selector The channel selector selects one of the input ports P17/AN7-P10/ AN0. 8-bit reading (Read only address 003716) b7 (address 003716) b0 b9 b8 b7 b6 b5 b4 b3 b2 Fig. 103 10-bit A/D mode reading Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 73 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Data bus AD control register (address 003616) b7 b0 3 P10/DQ0/AN0 P11/DQ1/AN1 P12/DQ2/AN2 P13/DQ3/AN3 P14/DQ4/AN4 P15/DQ5/AN5 P16/DQ6/AN6 P17/DQ7/AN7 A/D control circuit Channel selector A/D interrupt request AD conversion register 2 (address 003816) (address 003716) Comparator AD conversion register 1 10 Resistor ladder VREF Fig. 104 A/D converter block diagram VSS Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 74 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control register (address 003916) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 003916) may be started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit (bit 6), and watchdog timer H count source selection bit (bit 7) are read. qWatchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at system clock 8 MHz frequency. When this bit is set to "1", the count source becomes the system clock divided by 16. The detection time in this case is set to 512 s at system clock 8 MHz frequency. This bit is cleared to "0" after resetting. qOperation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled. Once the STP instruction is executed, an internal reset occurs. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting. Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to "FF16." "FF16" is set when watchdog timer control register is written to. Data bus "FF16" is set when watchdog timer control register is written to. System clock Watchdog timer L (8) 1/16 "0" "1" Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction disable bit STP instruction RESET Reset circuit Internal reset Fig. 105 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 003916) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: System clock/16 Fig. 106 Structure of Watchdog timer control register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 75 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 16 cycles or more of XIN. Then the RESET pin is returned to an "H" level (the power source voltage should be between 3.0 V and 5.25 V for L version, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is under 0.6 V for VCC of 3.0 V (L version). Poweron Power source voltage 0V (Note) RESET VCC Reset input voltage 0V 0.2VCC Note : Reset release voltage ; Vcc = 3.0 V (L version) RESET VCC Power source voltage detection circuit Fig. 107 Example of reset circuit XIN RESET Internal reset Address ? ? ? ? FFFC F FFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 108 Reset sequence Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 76 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION PLL CIRCUIT (FREQUENCY SYNTHESIZER) The PLL circuit generates fVCO (PLL output clock), which is required for fUSB (USB clock) and fSYN (fUSB division clock), from f(XIN) (external input reference clock). Figure 109 shows the PLL circuit block diagram. It is possible to input 6 or 12 MHz clock from the externals as a standard clock input. When using the USB function, set the PLL operation mode selection bit so that fvco may be set to 48 MHz. The PLL circuit operates by setting the PLL operation enable bit to "1". When supplying fVCO to the USB block, wait for the oscillation stable time (1ms or less) of PLL before selecting fVCO with the USB clock selection bit. According to the setting of the USB clock division ratio selection bit, the division clock of fUSB is supplied to fSYN. When using this clock as system clock, set the USB clock division ratio selection bit so that it may be set to 6 MHz, 8 MHz or 12 MHz. (However, using it only when fUSB is 48MHz is recommended). fUSB f(XIN) PLL fVCO Division circuit fSYN PLLCON (address 0FF816) USBCON (address 001016) Fig. 109 Block diagram of PLL circuit Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 77 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 PLL control register (PLLCON: address 0FF816) Not used (return "0" when read) USB clock division ratio selection bits b4b3 0 0: Divided by 8 (fSYN = fUSB/8) 0 1: Divided by 6 (fSYN = fUSB/6) 1 0: Divided by 4 (fSYN = fUSB/4) 1 1: Not selected PLL operation mode selection bits b6b5 0 0: Not multiplied (fVCO = fXIN) 0 1: Double (fVCO = fXIN 2) 1 0: Quadruple (fVCO = fXIN 4) 1 1: Multiplied by 8 (fVCO = fXIN 8) PLL Enable Bit 0: Disabled 1: Enabled Fig. 110 Structure of PLL control register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 78 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION CLOCK GENERATING CIRCUIT An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and the XIN oscillator stops. When the oscillation stabilizing time set after STP instruction released bit is "0," the prescaler 12 is set to "FF16" and timer 1 is set to "0116." When the oscillation stabilizing time set after STP instruction released bit is "1," set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. XIN divided by 16 is compulsorily connected to the input of the prescaler 12. Oscillator restarts when an external interrupt (including USB resume interrupt) is received, but the internal clock remains at "H" until timer 1 underflows. The internal clock is not supplied until timer 1 underflows. Because the sufficient time is required for the oscillation to stabilize when a ceramic resonator etc. is used. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated automatically. Frequency Control Either fSYN or f(XIN) can be selected as an internal system clock. Furthermore, the frequency of internal clock can be selected by the system clock division ratio selection bit. (1) fSYN clock fSYN clock is generated by the PLL circuit. f(XIN) or fVCO can be selected as an input clock. When using as an internal system clock, there is restriction on use. Refer to the clause of "PLL CIRCUIT". (2) f(XIN) clock The frequency applied to the XIN pin is used as an internal system clock frequency. (2) Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to "1" before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to "0" before executing the STP instruction. sNote When using the oscillation stabilizing time set after STP instruction released bit set to "1", evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 79 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION b7 b0 XIN XOUT Rd (Note) MISRG (MISRG: address 0FFB16) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set nothing Not used (indefinite at read) CIN COUT Note : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig. 113 Structure of MISRG Fig. 111 Ceramic resonator or quartz-crystal oscilltor circuit XIN XOUT Open External oscillation circuit VCC VSS Fig. 112 External clock input circuit XIN XOUT PLL fvco USB clock selection bit fUSB 1/4 1/6 1/8 USB clock division ration selection bits fSYN System clock selection bit fsio fAD 1/2 1/1 1/2 1/2 1/4 1/2 1/8 1/2 Prescaler 12 Timer 1 Reset or STP FF16 System clock division ration selection bits 0116 instruction Timing (internal clock) QS R Reset Interrupt disable flag l Interrupt request STP instruction WIT instruction SQ R QS R STP instruction Reset Fig. 114 System clock generating circuit block diagram (single-chip mode) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 80 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Reset XIN 8-divide mode f() = 0.75 MHz CM7 = 0 CM6 = 0 CM5 = 0 PLLCON [4:3] = 00 CM6 "0""1" XIN 4-divide mode f() = 1.5 MHz CM7 = 0 CM6 = 0 CM5 = 0 PLLCON [4:3] = xx (arbitrary) C "0 M6 C M " "1 7 " 1" " "0 " " 6 "1 CM " 1" "0 M7 " C " "0 CM7 "1""0" XIN 2-divide mode f() = 3.0 MHz CM 7 = 1 CM 6 = 0 CM 5 = 0 PLLCON [4:3] = xx (arbitrary) CM6 "0""1" XIN through mode f() = 1.5 MHz CM7 = 0 CM6 = 0 CM5 = 0 PLLCON [4:3] = xx (arbitrary) CM5 "1""0" Note: Set PLLCON [4:3] = 10 before switching the system clock from XIN to fSYN. f(SYN) 2-divide mode f() = 6.0 MHz CM 7 = 1 CM 6 = 0 CM 5 = 1 PLLCON [4:3] = 10 CM6 "0""1" f(SYN) through mode f() = 12.0 MHz CM7 = 1 CM6 = 1 CM5 = 1 PLLCON [4:3] = 10 CM5 "0""1" CM6 "0""1" Note: Set PLLCON [4:3] = 00 before switching the system clock from XIN to fSYN. Under planning f(SYN) through mode f() = 6.0 MHz CM7 = 1 CM6 = 1 CM5 = 1 PLLCON [4:3] = 00 CM5 "1""0" CM7 "1""0" CM5 "0""1" Note: Set PLLCON [4:3] = 00 before switching the system clock from XIN to fSYN. CM5 "0""1" CM6 "0""1" Note: Set PLLCON [4:3] = 01 before switching the system clock from XIN to fSYN. f(SYN) through mode f() = 8.0 MHz CM7 = 1 CM6 = 1 CM5 = 1 PLLCON [4:3] = 01 CM5 "0""1" Note: Set PLLCON [4:3] = 01 before switching the system clock from XIN to fSYN. Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN. 3 : Do not change a division ratio of USB clock when using fSYN as the system clock. 4 : See section "PLL CIRCUIT" in details for enabling/disabling PLL operation and usage notes of fSYN. 5 : Set the system clock to XIN when entering STOP mode. 6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In WAIT mode the timers can operate. Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin. Fig. 115 State transitions of clock Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 81 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION FLASH MEMORY MODE The 38K0 group's flash memory version has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 4.5 to 5.25 V, and 2 power sources when VCC is 3.0 to 4.5 V. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Summary Table 8 lists the summary of the 38K0 group's flash memory version. This flash memory version has some blocks on the flash memory as shown in Figure 116 and each block can be erased. The flash memory is divided into User ROM area and Boot ROM area. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user's application system. This Boot ROM area can be rewritten in only parallel I/O mode. Table 8 Summary of 38K0 group's flash memory version Item Power source voltage (Vcc) Program/Erase VPP voltage (VPP) Flash memory mode Specifications 3.00 - 5.25 V (L version) (Program and erase in 4.00 to 5.25 V of Vcc.) 3.00 - 4.00 V (L version) (Program and erase in 3.00 to 5.25 V of Vcc.) 4.50 - 5.25 V 3 modes; Flash memory can be manipulated as follows: *CPU rewrite mode: Manipulated by the Central Processing Unit (CPU). *Parallel I/O mode: Manipulated using an external programmer (Note 1) Erase block division User ROM area Boot ROM area *Standard serial I/O mode: Manipulated using an external programmer (Note 1) 1 block (32 Kbytes) 1 block (4 Kbytes) (Note 2) Byte program Batch erasing Program/Erase control by software command 6 commands 100 times 10 years Available in parallel I/O mode and standard serial I/O mode Program method Erase method Program/Erase control method Number of commands Number of program/Erase times Data retention period ROM code protection Notes 1: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 38K0 Group (flash memory version). 2: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 82 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 116 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be executed before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 116 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P16 (CE) pin high, the CNVSS pin high, the CPU starts operating using the control program in the Boot ROM area. This mode is called the "Boot" mode. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. User ROM area 800016 FFFF16 Block 1 : 32 Kbytes F00016 FFFF16 Boot ROM area 4 Kbytes Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Fig. 116 Block diagram of built-in flash memory Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 83 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to a memory such as the internal RAM before it can be executed. The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V to the CNVSS pin and setting "1" to the CPU Rewrite Mode Select Bit (bit 1 of address 0FFE16). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 117 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0" (busy). Otherwise, it is "1" (ready). This is equivalent to the RY/BY pin function in parallel I/O mode. Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to "1", the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in a memory other than internal flash memory for write to bit 1. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. The bit can be set to "0" by only writing "0". Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates "1" in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is "1", setting "1" for this bit resets the control circuit. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. To release the reset, it is necessary to set this bit to "0". Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to "1", Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to "1" automatically. Reprogramming of this bit must be in a memory other than internal flash memory. Figure 118 shows a flowchart for setting/releasing CPU rewrite mode. b7 b0 Flash memory control register (address 0FFE16) FMCR (Note 1) RY/BY status flag 0: Busy (being written or erased) 1: Ready CPU rewrite mode select bit (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag 0: Normal mode (Software commands invalid) 1: CPU rewrite mode Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User area / Boot area select bit (Note 4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (indefinite at read/ "0" at write) Notes 1: The contents of flash memory control register are "XXX00001" just after reset release. 2: For this bit to be set to "1", the user needs to write "0" and then "1" to it in succession. If it is not this procedure, this bit will not be set to "1". Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is "1". Set this bit 3 to "0" subsequently after setting bit 3 to "1". 4: Use the control program in the area except the built-in flash memory for write to this bit. Fig. 117 Structure of flash memory control register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 84 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Start Single-chip mode or Boot mode (Note 1) Set CPU mode register (Note 2) Transfer CPU rewrite mode control program to memory other than internal flash memory Jump to control program transferred in memory other than internal flash memory (Subsequent operations are executed by control program in this memory) Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession) Check CPU rewrite mode entry flag Using software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 3) Write "0" to CPU rewrite mode select bit End Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply 4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set the system clock division ration selection bits of CPU mode register (bits 6 and 7 at address 003B16). 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. Fig. 118 CPU rewrite mode set/release flowchart Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 85 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode. qOperation speed During CPU rewrite mode, set the internal clock to 1.5 MHz or less using the system clock division ratio selection bits (bits 6 and 7 of address 003B16). qInstructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . qInterrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. qWatchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. qReset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVss = "H", so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 86 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Software Commands Table 9 lists the software commands. After setting the CPU Rewrite Mode Select Bit to "1", write a software command to specify an erase or program operation. Each software command is explained below. qRead Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained intact until another command is written. qRead Status Register Command (7016) When the command code "7016" is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. qClear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle. qProgram Command (4016) Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, the control circuit of flash memory (data programming and verification) will start a program. Whether the write operation is completed can be confirmed by _____ reading the status register or the RY/BY Status Flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (DB0 to DB7). The status register bit 7 (SR7) is set to "0" at the same time the write operation starts and is returned to "1" upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written. Table 9 List of software commands (CPU rewrite mode) ____ During the program movement, The RY/BY Status Flag of flash memory control register is set to "0". When the program completes, it becomes "1". At program end, program results can be checked by reading the status register. Start Write 4016 Write Write address Write data Status register read SR7 = 1 ? or RY/BY = 1 ? YES NO SR4 = 0 ? YES Program completed NO Program error Fig. 119 Program flowchart Command Read array Read status register Clear status register Program Erase all blocks Block erase Cycle number 1 2 1 2 2 2 Mode Write Write Write Write Write Write First bus cycle Data Address (D0 to D7) X (Note 4) Second bus cycle Data Mode Address (D0 to D7) FF16 7016 5016 4016 2016 2016 Write Write Write BA WA (Note 2) X (Note 3) X X X X X Read X SRD (Note 1) WD (Note 2) 2016 D016 Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address to be erased (Input the maximum address of each block.) 4: X denotes a given address in the User ROM area . Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 87 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qErase All Blocks Command (2016/2016) By writing the command code "2016" in the first bus cycle and the confirmation command code "2016" in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY Status Flag of flash memory control register. When the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (D0 to D7). The status register bit 7 (SR7) is set to "0" at the same time the erase operation starts and is returned to "1" upon completion of the erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY Status Flag is "0" during erase operation and "1" when the erase operation is completed as is the status register bit 7. After the erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. qBlock Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time the block erase operation starts and is returned to "1" upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY Status Flag is "0" during block erase operation and "1" when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Start Write 2016 Write 2016/D016 Block address 2016:Erase all blocks D016:Block erase Status register read SR7 = 1 ? or RY/BY = 1 ? NO YES NO SR5 = 0 ? Erase error YES Erase completed Fig. 120 Erase flowchart Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 88 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to "8016". Table 10 shows the status register. Each bit in this register is explained below. *Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to "0" (busy) during write or erase operation and is set to "1" when these operations ends. After power-on, the sequencer status is set to "1" (ready). *Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". *Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to "1". The program status is set to "0" when it is cleared. If "1" is written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Table 10 Definition of each bit in status register Each bit of SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition "1" Ready Terminated in error Terminated in error - "0" Busy Terminated normally Terminated normally - Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 89 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 121 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (block erase, program) Note: When one of SR5 and SR4 is set to "1", none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 121 Full status check flowchart and remedial procedure for errors Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 90 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. qROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control register (address FFDB16) in parallel I/O mode. Figure 122 shows the ROM code protect control register (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to "0", the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to "00", the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits. b7 b0 ROM code protect control register (address FFDB16) ROMCP Reserved bits ("1" at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (Note 3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode. Fig. 122 Structure of ROM code protect control register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 91 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD416 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM cord protect control Interrupt vector area Fig. 123 ID code store addresses Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 92 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the 38K0 Group (flash memory version). Refer to each programmer maker's handling manual for the details of the usage. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 116 can be rewritten. Both areas of flash memory can be operated on in the same way. The boot ROM area is 4 Kbytes in size. It is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial I/O mode, you must perform program and block erase in the user ROM area. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 93 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION (3) Standard Serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific peripheral unit.The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting "H" to the P16 (CE) pin and "H" to the P42 (SCLK) pin and "H" to the CNVSS (VPP) pin (apply 4.5 V to 5.25 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to "L" level.) This control program is written in the Boot ROM area when the product is shipped from Renesas Technology Corp.. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figure 124 shows the pin connections for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four serial I/O pins SCLK, RxD, TxD and SRDY (BUSY). The SCLK pin is the transfer clock input pin through which an external transfer clock is input. The TxD pin is for CMOS output. The SRDY (BUSY) pin outputs "L" level when ready for reception and "H" level when reception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 116 can be rewritten. The Boot ROM area cannot. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Outline Performance (Standard Serial I/O Mode) In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK pin, and are then input to the MCU via the RxD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD pin. The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the SRDY (BUSY) pin is "H" level. Accordingly, always start the next transfer after the SRDY (BUSY) pin is "L" level. Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 94 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Table 11 Description of pin function (Standard Serial I/O Mode) Pin name VCC,VSS VCCE CNVSS CNVSS2 VREF DVCC, PVCC PVSS ____________ RESET XIN XOUT USBVREF TrON D0+,D0P00 to P07 P10 to P15 P16 P17 P20 to P27 P30 to P37 P40 P41 P42 P43 P50 to P57 P60 to P63 Signal name Power supply Power supply VPP CNVSS2 Analog reference voltage Analog power supply Analog power supply Reset input Clock input Clock output USB reference voltage input USB reference voltage output USB upstream input Input port P0 Input port P1 Input port P1 Input port P1 Input port P2 Input port P3 RxD input TxD output SCLK input BUSY output Input port P5 Input port P6 I/O Function Apply 3.00 to 5.25 V (L version) to the Vcc pin and 0 V to the Vss pin. Connect this pin to Vcc. Connect this pin to VPP (VPP = 4.50 to 5.25 V). Connect this pin to Vss. Connect this pin to Vcc when not using. Connect this pin to Vcc. Connect this pin to Vss. To reset, input "L" level for 20 cycles or longer clocks of . Connect a ceramic or crystal resonator between the XIN and XOUT pins. When entering an externally drived clock, enter it from XIN and leave XOUT open. Connect this pin to Vcc when not using. Leave this pin open when not using. Input "L" level when not using. Input "L" or "H" level, or keep open. Input "L" or "H" level, or keep open. Input "L" or "H" level, or keep open. Input "H" level only at release of reset. Input "L" or "H" level, or keep open. Input "L" or "H" level, or keep open. Input "L" or "H" level, or keep open. This is a serial data input pin. This is a serial data output pin. This is a serial clock input pin.Input "H" level only at release of reset. This is a BUSY output pin. Input "L" or "H" level, or keep open. Input "L" or "H" level, or keep open. I I I I I O O I/O I I I I I I I O I O I I Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 95 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION P05 P04 P03 P02 P01 P00 P57 P56 P55 P54 P53 P52/INT1 P51/CNTR0 P50/INT0 P27 P26 Vcc Vss 36 35 44 43 42 40 39 38 37 34 33 47 46 45 48 41 RXD TXD SCLK BUSY P06 P07 P40/EXDREQ/RXD P41/EXDACK/TXD P42/EXTC/SCLK P43/EXA1/SRDY P30 P31 P32 P33/EXINT P34/EXCS P35/EXWR P36/EXRD P37/EXA0 P10/DQ0/AN0 P11/DQ1/AN1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 13 14 8 9 10 11 12 15 16 1 4 5 6 7 2 3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 M38K09F8LFP/HP P25 P24 P23 P22 P21 P20 D0D0+ TrON USBVREF DVCC PVCC PVSS P63(LED3) P62(LED2) P61(LED1) Mode setup method Signal CNVss SCLK RESET CE Value 4.5 to 5.25 V Vcc (Note 2) Vss Vcc Vcc (Note 2) (Note 1) Notes 1: Connect to Vcc in the case of Vcc = 4.5 V to 5.25 V. Connect to VPP (= 4.5 V to 5.25 V) in the case of Vcc = 3.0 V to 4.5 V. 2: Supply Vcc at releasimg Reset. Package outline: PLQP0064GA-A, PLQP0064KB-A Fig. 124 Pin connection diagram in standard serial I/O mode (1) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 96 of 112 VPP RESET CE P12/DQ2/AN2 P13/DQ3/AN3 P14/DQ4/AN4 P15/DQ5/AN5 P16/DQ6/AN6 P17/DQ7/AN7 CNVSS RESET VCCE VREF VSS XIN XOUT VCC CNVSS2 P60(LED0) Connect to oscillator circuit. HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Software Commands Table 12 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software commands via the RxD pin. Software commands are explained Table 12 Software commands (Standard serial I/O mode) Control command 1 Page read 1st byte transfer FF16 2nd byte Address (middle) Address (middle) D016 SRD output SRD1 output 3rd byte Address (high) Address (high) here below. Basically, the software commands of the standard serial I/O mode are the same as that of the parallel I/O mode, but the block erase function is excluded, and 4 commands are added: ID check, download, version data output and Boot ROM area output functions. 4th byte Data output Data input 5th byte Data output Data input 6th byte Data output Data input ..... Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable Not acceptable 2 Page program 4116 3 4 5 6 7 Erase all blocks Read status register Clear status register ID check function Download function A716 7016 5016 F516 FA16 Address (low) Size (low) Address (middle) Size (high) Address (high) Checksum ID size Data input ID1 To required number of times Version data output Data output To ID7 Acceptable Not acceptable 8 Version data output function FB16 9 Boot ROM area output function FC16 Version data output Address (middle) Version data output Address (high) Version data output Data output Version data output Data output Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from a programmer to the internal flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted when the flash memory is totally blank. 4: Address low is A0 to A7; Address middle is A8 to A15; Address high is A16 to A23. Address-high A16 to A23 are always "0016". Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 97 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION The contents of software commands are explained as follows. qPage Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK RxD FF16 A8 to A15 A16 to A23 TxD data0 data255 SRDY (BUSY) Fig. 125 Timing for page read qRead Status Register Command This command reads status information. When the "7016" command code is transferred with the 1st byte, the contents of the status register (SRD) with the 2nd byte and the contents of status register 1 (SRD1) with the 3rd byte are read. SCLK RxD 7016 TxD SRD output SRD1 output SRDY (BUSY) Fig. 126 Timing for reading status register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 98 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qClear Status Register Command This command clears the bits (SR3 to SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY (BUSY) signal changes from "H" to "L" level. SCLK RxD 5016 TxD SRDY (BUSY) Fig. 127 Timing for clear status register qPage Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0 to D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the SRDY (BUSY) signal changes from "H" to "L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. SCLK RxD 4116 A8 to A15 A16 to data0 A23 data255 TxD SRDY (BUSY) Fig. 128 Timing for page program Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 99 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qErase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When erase all blocks end, the SRDY (BUSY) signal changes from "H" to "L" level. The result of the erase operation can be known by reading the status register. SCLK RxD A716 D016 TxD SRDY (BUSY) Fig. 129 Timing for erase all blocks Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 100 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qDownload Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. SCLK RxD FA16 Data size Data size (low) (high) Check sum Program data TxD Program data SRDY (BUSY) Fig. 130 Timing for download Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 101 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qVersion Information Output Command This command outputs the version information of the control program stored in the Boot ROM area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. SCLK RxD FB16 TxD `V' `E' `R' `X' SRDY (BUSY) Fig. 131 Timing for version information output qBoot ROM Area Output Command This command reads the control program stored in the Boot ROM area in page (256 bytes) unit. Execute the Boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK RxD FC16 A8 to A15 A1 6 to A23 TxD data0 data255 SRDY (BUSY) Fig. 132 Timing for Boot ROM area output Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 102 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 ("0016") of the 1st byte of the ID code with the 2nd, 3rd and 4th respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) Transfer the ID code with the 6th byte onward, starting with the 1st byte of the code. SCLK RxD F516 D416 FF16 0016 ID size ID1 ID7 TxD SRDY (BUSY) Fig. 133 Timing for ID check qID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFD416 to FFDA16. Write a program into the flash memory, which already has the ID code set for these addresses. Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 134 ID code storage addresses Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 103 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qStatus Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 13 lists the definition of each status register bit. After releasing the reset, the status register becomes "8016". *Sequencer status (SR7) The sequencer status indicates the operating status of the the flash memory. After power-on and recover from deep power down mode, the sequencer status is set to "1" (ready). This status bit is set to "0" (busy) during write or erase operation and is set to "1" upon completion of these operations. *Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". *Program status (SR4) The program status indicates the operating status of write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0". Table 13 Status register (SRD) Definition SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error - "0" Busy Terminated normally Terminated normally - Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 104 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION qStatus Register 1 (SRD1) The status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 14 lists the definition of each status register 1 bit. This register becomes "0016" when power is turned on and the flag status is maintained even after the reset. *Boot update completed bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. *Check sum consistency bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. *ID check completed bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. *Data reception time out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command wait state. Table 14 Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Definition "1" Update completed Match 00 01 10 11 "0" Not Update Mismatch Not verified Verification mismatch Reserved Verified Normal operation - SR9 (bit1) SR8 (bit0) Data reception time out Reserved Time out - Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 105 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 135 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (Erase, program) Note: When one of SR5 to SR4 is set to "1" , none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 135 Full status check flowchart and remedial procedure for errors Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 106 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION Example Circuit Application for Standard Serial I/O Mode Figure 136 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. VCC VCC Clock input BUSY output Data input Data output SCLK SRDY (BUSY) RxD TxD P16 (CE) M38K09F8L VPP power source input CNVss Notes 1: Control pins and external circuitry will vary according to a programmer. For more information, see the programmer manual. 2: In this example, the VPP power supply is supplied from an external source (programmer). To use the user's power source, connect to 4.5 V to 5.25 V. Fig. 136 Example circuit application for standard serial I/O mode Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 107 of 112 HARDWARE 38K0 Group NOTES ON PROGRAMMING NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. However, When using the USB function or EXB function, an occurrence of one-wait due to the multichannel RAM will double an internal clock cycle. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers * When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X is switched, stop a count of timer X. Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. A/D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(system clock) in the middle/highspeed mode is at least on 500 kHz during an A/D conversion. Do not execute the STP or WIT instruction during an A/D conversion. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 108 of 112 HARDWARE 38K0 Group NOTES ON PROGRAMMING Definition of A/D Conversion Accuracy The A/D conversion accuracy is defined below (refer to Figure 137). *Relative accuracy Zero transition voltage (VOT) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." Non-linearity error This means a deviation from the line between VOT and VFST of a converted value between VOT and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converted value between VOT and VFST by 1 LSB of the 1 LSB at the relative accuracy. *Absolute accuracy This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion characteristics. Output data Full-scale transition voltage (VFST) 1023 1022 Differential non-linearity error= c Non-linearity error= a [LSB] b-a a [LSB] b a n+1 n Actual A/D conversion characteristics c a: 1LSB at relative accuracy b: Vn+1-Vn c: Difference between the ideal Vn and actual Vn Ideal line of A/D conversion between V0 to V1022 1 0 V0 V1 Zero transition voltage (V0T) Vn Vn+1 V1022 Analog voltage VREF Fig. 137 Definition of A/D conversion accuracy Vn: Analog input voltage when the output data changes from "n" to "n + 1" (n = 0 to 1022) VFST - VOT 1022 VREF * 1 LSB at absolute accuracy 1024 * 1 LSB at relative accuracy (V) (V) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 109 of 112 HARDWARE 38K0 Group NOTES ON USAGE/DATA REQUIRED FOR MASK ORDERS NOTES ON USAGE Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. USB Communication In applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. Flash Memory Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic or electrolytic capacitor of 1.0 F is recommended. Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. USB Port Pins (D0+, D0-) Treatment *The USB specification requires a driver-impedance 28 to 44 . In order to meet the USB specification impedance requirements, connect a resistor (27 recommended) in series to the USB port pins. In addition, in order to reduce the ringing and control the falling/ rising timing and a crossover point, connect a capacitor between the USB port pins and the Vss pin if necessary. The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. *Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the USB lines. Also, make sure you use a USB specification compliant connecter for the connection. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com). USBVREF pin Treatment (Noise Elimination) *Connect a capacitor between the USBVREF pin and the Vss pin. The capacitor should have a 2.2 F capacitor (electrolytic capacitor) and a 0.1 F capacitor (ceramic type capacitor) connected in parallel. *In Vcc = 3.0 to 3.6 V operation, connect the USBVREF pin directly to the Vcc pin in order to supply power to the USB port circuit. In addition, you will need to disable the built-in USB reference voltage circuit in this operation (set bit 4 of the USB control register to "0".) If you are using the bus powered supply in this condition, the DC-DC converter must be placed outside the MCU. *In Vcc = 4.00 to 5.25 V operation, do not connect the external DC-DC converter to the USBVREF pin. Use the built-in USB reference voltage circuit. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 110 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT A/D Converter A/D conversion is started by setting AD conversion completion bit to "0." During A/D conversion, internal operations are performed as follows. 1. After the start of A/D conversion, AD conversion register goes to "0016." 2. The highest-order bit of AD conversion register is set to "1," and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of AD conversion register becomes "1." When Vref > VIN, the highest-order bit becomes "0." By repeating the above operations up to the lowest-order bit of the AD conversion register, an analog value converts into a digital value. A/D conversion completes at 122 clock cycles (15.25 s at system clock = 8 MHz, Through mode) after it is started, and the result of the conversion is stored into the AD conversion register. Concurrently with the completion of A/D conversion, A/D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to "1." Table 15 Relative formula for a reference voltage VREF of A/D converter and Vref When n = 0 When n = 1 to 1023 Vref = 0 Vref = VREF n 1024 n: Value of A/D converter (decimal numeral) Table 16 Change of AD conversion register during A/D conversion Change of AD conversion register At start of conversion First comparison Second comparison Third comparison Value of comparison voltage (Vref) 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF 2 VREF 2 VREF 2 0 VREF 4 VREF 4 VREF 8 1 2 After completion of tenth comparison A result of A/D conversion 1 2 3 4 5 6 7 8 9 0 1 VREF 2 VREF 4 **** VREF 1024 1-10: A result of the first comparison to the tenth comparison Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 111 of 112 HARDWARE 38K0 Group FUNCTIONAL DESCRIPTION SUPPLEMENT Figures 138 shows the A/D conversion equivalent circuit, and Figure 139 shows the A/D conversion timing chart. VCC About 2 kW AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VSS VIN Sampling clock VCC VSS C Chopper amplifier AD conversion register 2 AD conversion register 1 b2 b1 b0 AD control register AD conversion interrupt request VREF Built-in D/A converter Vref Reference clock VSS Fig. 138 A/D conversion equivalent circuit Write signal for AD control register 61 cycles AD conversion completion bit Sampling clock Fig. 139 A/D conversion timing chart Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 112 of 112 CHAPTER 2 APPLICATION 2.1 I/O port 2.2 Interrupt 2.3 Timer 2.4 Serial I/O 2.5 USB function 2.6 External bus interface (EXB) 2.7 A/D converter 2.8 Watchdog timer 2.9 Reset 2.10 Frequency synthesizer (PLL) 2.11 Clock generating circuit 2.12 Standby function 2.13 Flash memory APPLICATION 38K0 Group 2.1 I/O port 2.1 I/O port This paragraph explains the registers setting method and the notes related to the I/O ports. 2.1.1 Memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 0FF016 0FF216 Port P0 pull-up control register (PULL0) Port P5 pull-up control register (PULL5) Fig. 2.1.1 Memory map of registers related to I/O port Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 2 of 111 APPLICATION 38K0 Group 2.1 I/O port 2.1.2 Related registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) (Note) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16] B 0 Port Pi0 1 Port Pi1 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins At reset RW ? ? ? ? ? ? ? ? q 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Note: Since the following ports are not allocated, the corrrsponding bits can not be used. * P44 to P47 * P64 to P67 Fig. 2.1.2 Structure of Port Pi (i = 0 to 6) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) (Note) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset RW 0 Port Pi direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note: Since the following ports are not allocated, the corrrsponding bits can not be used. * P44 to P47 * P64 to P67 Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 3 of 111 APPLICATION 38K0 Group 2.1 I/O port Port P0 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 pull-up control register (PULL0) [Address : 0FF016] B 0 1 2 3 4 5 Name P00 pul l-up control bit P00 pul l-up control bit P00 pul l-up control bit P00 pul l-up control bit P00 pul l-up control bit P00 pul l-up control bit Function 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up At reset RW 0 0 0 0 0 0 0 0 6 P00 pul l-up control bit 7 P00 pul l-up control bit Fig. 2.1.4 Structure of Port P0 pull-up control register Port P5 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 pull-up control register (PULL5) [Address : 0FF216] B Name Function 0 : No pull-up 1 : Pull-up At reset RW 0 P50 pul l-up control bit 1 0 0 0 0 0 0 0 0 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0". 2 P52 pul l-up control bit 3 4 5 6 7 0 : No pull-up 1 : Pull-up Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". Fig. 2.1.5 Structure of Port P5 pull-up control register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 4 of 111 APPLICATION 38K0 Group 2.1 I/O port 2.1.3 Handling of unused pins Table 2.1.1 Handling of unused pins Handling Pins/Ports name P0, P1, P2, P3, P4, *Set to the input mode and connect each to Vcc or Vss through a resistor of 1 k to 10 k. P5, P6 *Set to the output mode and open at "L" or "H" level. VREF XOUT USBVREF TrON D0+, D0*Connect to Vss (GND). *Open, only when using an external clock. *Connect to VCC *Open *Connect each to Vss through a resistor of 1 k to 10 k. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 5 of 111 APPLICATION 38K0 Group 2.1 I/O port 2.1.4 Notes on input and output pins (1) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*1, the value of the unspecified bit may be changed. q Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. * As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing. * As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following : * Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. * As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 1 bit managing instructions : SEB, and CLB instructions Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 6 of 111 APPLICATION 38K0 Group 2.1 I/O port 2.1.5 Termination of unused pins (1) Terminate unused pins I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. With regard to ports which can select the built-in pull-up resistor, the built-in pullup resistor can be used. Set the I/O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks I/O ports : Do not open in the input mode. q Reason * The power source current may increase depending on the first-stage circuit. * An effect due to noise may be easily produced as compared with proper termination shown in (1). I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 7 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2 Interrupt This paragraph explains the registers setting method and the notes related to the interrupt. 2.2.1 Memory map 003C16 003D16 003E16 003F16 Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FF316 Interrupt edge selection register (INTEDGE) Fig. 2.2.1 Memory map of registers related to interrupt 2.2.2 Related registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW USB bus reset 0 interrupt request bit 0 0 0 0 0 0 0 0 1 USB SOF interrupt request bit 2 USB device interrupt request bit 3 EXB interrupt request bit 4 request bit INT0 interrupt interrupt 5 Timer X bit request 6 request bit 7 request bit Timer 1 interrupt Timer 2 interrupt "0" can be set by software, but "1" cannot be set. Fig. 2.2.2 Structure of Interrupt request register 1 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 8 of 111 APPLICATION 38K0 Group 2.2 Interrupt Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued At reset RW INT1 interrupt 0 request bit 0 0 0 0 0 0 0 0 1 Nothing is arranged for this bits. This is a write disabled bit. When this bit is read out, the contents are "0". 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued receive 2 Serial I/Orequest bit interrupt transmit 3 Serial I/Orequest bit interrupt 4 request bit CNTR0 interrupt 5 Key-on wake-up bit interrupt request 6 7 A/D conversion interrupt request bit Nothing is arranged for this bits. This is a write disabled bit. When this bit is read out, the contents are "0". "0" can be set by software, but "1" cannot be set. Fig. 2.2.3 Structure of Interrupt request register 2 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16] B Name USB bus reset Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 interrupt enable bit 1 USB SOF interrupt enable bit 2 USB device interrupt enable bit 3 EXB interrupt enable bit 4 enable bit INT0 interrupt 0 0 0 0 0 0 0 0 interrupt 5 Timer Xbit enable 6 enable bit 7 enable bit Timer 1 interrupt Timer 2 interrupt Fig. 2.2.4 Structure of Interrupt control register 1 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 9 of 111 APPLICATION 38K0 Group 2.2 Interrupt Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Interrupt control register 2 (ICON2) [Address : 3F16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled At reset RW INT1 interrupt 0 enable bit 0 0 1 Fix this bit to "0". receive 2 Serial I/Oenable bit interrupt transmit 3 Serial I/Oenable bit interrupt 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 0 0 0 0 4 enable bit CNTR0 interrupt 5 Key-on wake-upbit interrupt enable 6 A/D conversion interrupt enable bit 7 Fix this bit to "0". Fig. 2.2.5 Structure of Interrupt control register 2 Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 0FF316] B 0 1 2 3 4 5 6 7 Name INT0 interrupt edge selection bit Function 0 : Falling edge active 1 : Rising edge active At reset RW 0 0 0 0 0 0 0 0 Nothing is arranged for this bits. This is a write disabled bit. When this bit is read out, the contents are "0". INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". Fig. 2.2.6 Structure of Interrupt edge selection register Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 10 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2.3 Interrupt source The 38K0 group permits interrupts of 15 sources. These are vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1. Table 2.2.1 Interrupt sources, vector addresses and priority of 38K0 group Interrupt Source Reset (Note 2) USB bus reset USB SOF USB device Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFFA16 FFF916 FFF716 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of USB bus reset signal (2.5 s interval SE0) At detection of USB SOF signal At detection of resume signal (K state or SE0) or suspend signal (3 ms interval bus idle), or at completion of transaction At completion of reception or transmission or at completion of DMA transmission At detection of either rising or falling edge of INT0 input At timer X underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of INT1 input (Note 4) At completion of serial I/O data reception At completion of serial I/O data transmission At detection of either rising or falling edge of CNTR0 input At falling of conjunction of input level for port P0 (at input mode) At completion of A/D conversion At BRK instruction execution Remarks Non-maskable Valid when USB mode Valid when USB mode Valid when USB mode External bus 5 FFF516 FFF416 Valid when external bus is selected INT0 Timer X Timer 1 Timer 2 INT1 (Note 3) Serial I/O reception Serial I/O transmission CNTR0 Key-on wake up A/D conversion BRK instruction 6 7 8 9 10 -- 11 12 13 14 15 16 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 External interrupt (active edge selectable) STP release timer underflow External interrupt (active edge selectable) (Note 4) Valid when serial I/O is selected Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Nothing is arranged in these vector addresses. 4: Fix bit 1 of interrupt control register 2 (address 003F16) to "0". Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 11 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2.4 Interrupt operation When an interrupt request is accepted, the contents of the following registers just before acceptance of the interrupt requests is automatically pushed onto the stack area in the order of , and . High-order contents of program counter (PCH) Low-order contents of program counter (PCL) Contents of processor status register (PS) After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed. When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the above registers pushed onto the stack area are restored to the respective registers in the order of , and ; and the microcomputer resumes the processing executed just before acceptance of the interrupts. Figure 2.2.7 shows an interrupt operation diagram. Executing routine ******* Interrupt occurs (Accepting interrupt request) Suspended operation Contents of program counter (high-order) are pushed onto stack Contents of program counter (low-order) are pushed onto stack Contents of processor status register are pushed onto stack Interrupt processing routine RTI instruction Contents of processor status register are popped from stack Contents of program counter (low-order) are popped from stack Contents of program counter (high-order) are popped from stack Resume processing ******* : Operation commanded by software : Internal operation performed automatically Fig. 2.2.7 Interrupt operation diagram Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 12 of 111 APPLICATION 38K0 Group 2.2 Interrupt (1) Processing upon acceptance of interrupt request Upon acceptance of an interrupt request, the following operations are automatically performed. The processing being executed is stopped. The contents of the program counter and the processor status register are pushed onto the stack area. Figure 2.2.8 shows the changes of the stack pointer and the program counter upon acceptance of an interrupt request. Concurrently with the push operation, the jump destination address (the beginning address of the interrupt processing routine) of the occurring interrupt stored in the vector address is set in the program counter, then the interrupt processing routine is executed. After the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to "0". The interrupt disable flag is set to "1" so that multiple interrupts are disabled. Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination address in the vector area corresponding to each interrupt. Program counter PCL Program counter (low-order) PCH Program counter (high-order) Stack pointer S (S) Interrupt request is accepted Program counter PCL PCH Vector address (from Interrupt vector area) Stack pointer S (S) - 3 Interrupt disable flag = "1" (s) - 3 Interrupt disable flag = "0" (S) Stack area Stack area Processor status register Program counter (low-order) (S) Program counter (high-order) Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 13 of 111 APPLICATION 38K0 Group 2.2 Interrupt (2) Timing after acceptance of interrupt request The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently being executed. Figure 2.2.9 shows the time up to execution of interrupt processing routine and Figure 2.2.10 shows the timing chart after acceptance of interrupt request. Interrupt request generated Start of interrupt processing Main routine Waiting time for Stack push and post-processing of Vector fetch pipeline Interrupt processing routine 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (When f(XIN) = 6 MHz; system clock 8 MHz /through mode (8 MHz), 0.875 s to 2.875 s) When executing DIV instruction Fig. 2.2.9 Time up to execution of interrupt processing routine Waiting time for pipeline post-processing Push onto stack Vector fetch Interrupt operation starts SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH PCL PS SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116" Fig. 2.2.10 Timing chart after acceptance of interrupt request Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 14 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2.5 Interrupt control The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.11 shows an interrupt control diagram. Interrupt request bit Interrupt enable bit Interrupt request Interrupt disable flag BRK instruction Reset Fig. 2.2.11 Interrupt control diagram The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not affect each other. An interrupt is accepted when all the following conditions are satisfied. qInterrupt request bit .......... "1" qInterrupt enable bit ........... "1" qInterrupt disable flag ........ "0" Though the interrupt priority is determined by hardware, a variety of priority processing can be performed by software using the above bits and flag. Table 2.2.2 shows a list of interrupt control bits according to the interrupt source. (1) Interrupt request bits The interrupt request bits are allocated to the interrupt request register 1 (address 3C16) and interrupt request register 2 (address 3D16). The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to "1". The interrupt request bit is held in the "1" state until the interrupt is accepted. When the interrupt is accepted, this bit is automatically cleared to "0". Each interrupt request bit can be set to "0", but cannot be set to "1", by software. (2) Interrupt enable bits The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 3F16). The interrupt enable bits control the acceptance of the corresponding interrupt request. When an interrupt enable bit is "0", the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is "0", the corresponding interrupt request bit is set to "1" but the interrupt is not accepted. In this case, unless the interrupt request bit is set to "0" by software, the interrupt request bit remains in the "1" state. When an interrupt enable bit is "1", the corresponding interrupt is enabled. If an interrupt request occurs when this bit is "1", the interrupt is accepted (when interrupt disable flag = "0"). Each interrupt enable bit can be set to "0" or "1" by software. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 15 of 111 APPLICATION 38K0 Group 2.2 Interrupt (3) Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request except BRK instruction. When this flag is "1", the acceptance of interrupt requests is disabled. When the flag is "0", the acceptance of interrupt requests is enabled. This flag is set to "1" with the SEI instruction and is set to "0" with the CLI instruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to "1", so that multiple interrupts are disabled. To use multiple interrupts, set this flag to "0" with the CLI instruction within the interrupt processing routine. Figure 2.2.12 shows an example of multiple interrupts. Table 2.2.2 List of interrupt bits according to interrupt source Interrupt source USB bus reset USB SOF USB device External bus INT0 Timer X Timer 1 Timer 2 INT1 Serial I/O receive Serial I/O transmit CNTR0 Key-on wake-up A/D converter Interrupt enable bit Address 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003F16 003F16 003F16 003F16 003F16 003F16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b2 b3 b4 b5 b6 Interrupt request bit Address 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003D16 003D16 003D16 003D16 003D16 003D16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b2 b3 b4 b5 b6 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 16 of 111 APPLICATION 38K0 Group 2.2 Interrupt Interrupt request Nesting Reset Time Main routine I=1 C1 = 0, C2 = 0 Interrupt request 1 C1 = 1 I=0 Interrupt 1 Interrupt request 2 I=1 C2 = 1 I=0 Interrupt 2 I=1 RTI I=0 Multiple interrupt RTI I=0 I : Interrupt disable flag C1 : Interrupt enable bit of interrupt 1 C2 : Interrupt enable bit of interrupt 2 : Set automatically. : Set by software. Fig. 2.2.12 Example of multiple interrupts Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 17 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2.6 INT interrupt The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin (INT0, INT1). (1) Active edge selection INT0 and INT1 can be selected from either a falling edge or rising edge detection as an active edge by the interrupt edge selection register. In the "0" state, the falling edge of the corresponding pin is detected. In the "1" state, the rising edge of the corresponding pin is detected. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 18 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2.7 Key input interrupt A key input interrupt request is generated by applying "L" level to any port P0 pin that has been set to the input mode. In other words, it is generated when AND of the input level goes from "1" to "0". (1) Connection example when Key input interrupt is used When using the Key input interrupt, compose an active-low key matrix which inputs to port P0. Figure 2.2.13 shows a connection example and the port P0 block diagram when using a key input interrupt. In the connection example in Figure 2.2.13, a key input interrupt request is generated by pressing one of the keys corresponding to ports P00 to P03. Port PXx "L" level output PULL 0 register Bit 7 = "0" Port P07 direction register = "1" Port P07 latch Key input interrupt request P07 output PULL 0 register Bit 6 = "0" Port P06 direction register = "1" Port P06 latch P06 output PULL 0 register Bit 5 = "0" Port P05 direction register = "1" Port P05 latch P05 output PULL 0 register Bit 4 = "0" Port P04 direction register = "1" Port P04 latch P04 output PULL 0 register Bit 3 = "1" Port P03 direction register = "0" Port P03 latch Port P0 Input reading circuit P03 input PULL 0 register Bit 2 = "1" Port P02 direction register = "0" Port P02 latch P02 input PULL 0 register Bit 1 = "1" Port P01 direction register = "0" P01 input Port P01 latch PULL 0 register Bit 0 = "1" Port P00 direction register = "0" Port P00 latch P00 input P-channel transistor for pull-up CMOS output buffer Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 19 of 111 APPLICATION 38K0 Group 2.2 Interrupt (2) Related registers setting Figure 2.2.14 shows the related registers setting (corresponding to Figure 2.2.13). Port P0 direction register (address 0116) b7 b0 P0D 11110000 Bits corresponding to P07 to P00 0: Input port 1: Output port Port P0 pull-up control register (address 0FF016) b7 b0 PULL0 1111 P00 to P03 pull-up Interrupt request register 2 (address 3D16) b7 b0 IREQ2 0 Key-on wake-up interrupt request Interrupt control register 2 (address 3F16) b7 b0 ICON2 0 1 0 Key-on wake-up interrupt: Enabled Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 20 of 111 APPLICATION 38K0 Group 2.2 Interrupt 2.2.8 Notes on interrupts (1) Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to "1". When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. *Interrupt edge selection register (address 0FF316) *Timer X mode register (address 2316) Set the above listed registers or bits as the following sequence. Set the corresponding interrupt enable bit to "0" (disabled) . Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to "1". NOP (One or more instructions) Set the corresponding interrupt request bit to "0" (no interrupt request issued). Set the corresponding interrupt enable bit to "1" (enabled). Fig. 2.2.15 Sequence of changing relevant register s Reason When setting the following, the interrupt request bit may be set to "1". *When setting external interrupt active edge Concerned register: Interrupt edge selection register (address 0FF316) Timer X mode register (address 2316) Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 21 of 111 APPLICATION 38K0 Group 2.2 Interrupt (2) Check of interrupt request bit q When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to "0" by using a data transfer instruction, execute one or more instructions before executing the BBC or BBS instruction. Clear the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Data transfer instruction: LDM, LDA, STA, STX, and STY instructions Fig. 2.2.16 Sequence of check of interrupt request bit s Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to "0", the value of the interrupt request bit before being cleared to "0" is read. Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 22 of 111 APPLICATION 38K0 Group 2.3 Timer 2.3 Timer This paragraph explains the registers setting method and the notes related to the timers. 2.3.1 Memory map 002016 002116 002216 002316 002416 002516 003C16 003D16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TM) Prescaler X (PREX) Timer X (TX) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.3.1 Memory map of registers related to timers 2.3.2 Related registers Prescaler 12, Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12) [Address : 2016] Prescaler X (PREX) [Address : 2416] B Name Function At reset RW 0 *Set a count value of each prescaler. *The value set in this register is written to both each prescaler 1 and the corresponding prescaler latch at the same time. *When this register is read out, the count value of the corres2 ponding prescaler is read out. 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 2.3.2 Structure of Prescaler 12, Prescaler X Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 23 of 111 APPLICATION 38K0 Group 2.3 Timer Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2116] B Name Function At reset RW 0 *Set a count value of timer 1. *The value set in this register is written to both timer 1 and timer 1 1 latch at the same time. *When this register is read out, the timer 1's count value is read 2 out. 1 0 0 0 0 0 0 0 3 4 5 6 7 Fig. 2.3.3 Structure of Timer 1 Timer 2, Timer X b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address : 2216] Timer X (TX) [Address : 2516] Name B 0 *Set a count value of each timer. Function At reset RW 1 1 1 1 1 1 1 1 *The value set in this register is written to both each timer and 1 each timer latch at the same time. *When this register is read out, each timer's count value is read 2 out. 3 4 5 6 7 Fig. 2.3.4 Structure of Timer 2, Timer X Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 24 of 111 APPLICATION 38K0 Group 2.3 Timer Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TM) [Address : 2316] B Name b1 b0 Function 0 0 1 1 0 : Timer mode 1 : Pulse output mode 0 : Event counter mode 1 : Pulse width measurement mode At reset RW 0 Timer X operating mode bits 1 2 CNTR0 active edge selection bit 0 0 0 The function depends on the operating mode of Timer X. (Refer to Table 2.3.1) 0 : Count start 1 : Count stop 3 Timer X count stop bit 4 5 6 7 0 0 0 0 0 Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". Fig. 2.3.5 Structure of Timer X mode register Table 2.3.1 CNTR0 active edge selection bit function Timer X operation modes Timer mode CNTR0 active edge selection bit (bits 2 of address 2316) contents "0" CNTR0 interrupt request occurrence: Falling edge ; No influence to timer count "1" CNTR0 interrupt request occurrence: Rising edge ; No influence to timer count Pulse output mode "0" Pulse output start: Beginning at "H" level CNTR0 interrupt request occurrence: Falling edge "1" Pulse output start: Beginning at "L" level CNTR0 interrupt request occurrence: Rising edge Event counter mode "0" Timer X: Rising edge count CNTR0 interrupt request occurrence: Falling edge "1" Timer X: Falling edge count CNTR0 interrupt request occurrence: Rising edge Pulse width measurement mode "0" Timer X: "H" level width measurement CNTR0 interrupt request occurrence: Falling edge "1" Timer X: "L" level width measurement CNTR0 interrupt request occurrence: Rising edge Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 25 of 111 APPLICATION 38K0 Group 2.3 Timer Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW USB bus reset 0 interrupt request bit 0 0 0 0 0 0 0 0 1 USB SOF interrupt request bit 2 USB device interrupt request bit 3 EXB interrupt request bit 4 request bit INT0 interrupt interrupt 5 Timer X bit request 6 request bit 7 request bit Timer 1 interrupt Timer 2 interrupt "0" can be set by software, but "1" cannot be set. Fig. 2.3.6 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued At reset RW INT1 interrupt 0 request bit 0 0 0 0 0 0 0 0 1 Nothing is arranged for this bits. This is a write disabled bit. When this bit is read out, the contents are "0". 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued receive 2 Serial I/Orequest bit interrupt transmit 3 Serial I/Orequest bit interrupt 4 request bit CNTR0 interrupt 5 Key-on wake-up bit interrupt request 6 7 A/D conversion interrupt request bit Nothing is arranged for this bits. This is a write disabled bit. When this bit is read out, the contents are "0". "0" can be set by software, but "1" cannot be set. Fig. 2.3.7 Structure of Interrupt request register 2 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 26 of 111 APPLICATION 38K0 Group 2.3 Timer Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW USB bus reset 0 interrupt enable bit 0 0 0 0 0 0 0 0 1 USB SOF interrupt enable bit 2 USB device interrupt enable bit 3 EXB interrupt enable bit 4 enable bit INT0 interrupt interrupt 5 Timer Xbit enable 6 enable bit 7 enable bit Timer 1 interrupt Timer 2 interrupt Fig. 2.3.8 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Interrupt control register 2 (ICON2) [Address : 3F16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled At reset RW INT1 interrupt 0 enable bit 0 0 1 Fix this bit to "0". receive 2 Serial I/Oenable bit interrupt transmit 3 Serial I/Oenable bit interrupt 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 0 0 0 0 4 enable bit CNTR0 interrupt 5 Key-on wake-upbit interrupt enable 6 A/D conversion interrupt enable bit 7 Fix this bit to "0". Fig. 2.3.9 Structure of Interrupt control register 2 Rev.2.00 Oct 05, 2006 REJ09B0337-0200 page 27 of 111 APPLICATION 38K0 Group 2.3 Timer 2.3.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer 1, Timer 2) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
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